YouseKalack wrote:> the result of the sub operation is not the result expected.
What do you expect and wht do you get instead?
> My code
Pls use the [vhdl] tags further on to wrap your code!
See the "Formatting options" above each edit box...
> use ieee.std_logic_unsigned.all;> use ieee.numeric_std.all;
Never ever both together!
Otherwise you will encounter strange problems due to multiple type
YouseKalack wrote:> as you can see in the simulation ....
So setup a second test bench for your "cell" and have a look wether its
working as desired.
> I) The dataflow code to describe cell.
By looking at the picture bottom left corner a thought pops up in my
mind: shouldn't that "cell" also be described as a logic/structural
expression instead as a functional data flow description? And shouldn't
the CI be used for any operation in the "cell"?
To clear the view: the top left hand table is not related to the "cell"
driectly. That table shows the expected behaviour of the top level
Yousekalack wrote:> Yes the test work for one cell but only sub is not working good.. i> think the problem is when A = '0' and A - 1 = ???
No, for a single cell your code is also not working correctly.
Perform a simulation for a single cell. What are the correct outputs for
A=0, Cin=0 and opeartion A-1? What does your simulation show instead?
Huynh J. wrote:> Oper(1) is the carry out from all operations, i put'0' & but the '0'> will be replace if there is a carry
ok you're right, my mistake. "&" and "-" have identical priority and are
evaluted from left to right. So
'0' & Ai - '1'
('0' & Ai) - '1'
and then the higer bit (i.e. the carry) can indeed be set after the