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Forum: FPGA, VHDL & Verilog Arithmetic operator (Sub/Add/+1/-1) N bits Cascaded


von YouseKalack (Guest)


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Hello i've got a matter with my simulation, the result of the sub 
operation is not the result expected.

My code :

I) The dataflow code to describe cell.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity cell is 
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port(Ai,Bi,Ci : in std_logic;
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     S : in std_logic_vector (1 downto 0);
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     Co,Go : out std_logic);
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end cell;
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architecture dflow of cell is
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signal oper : std_logic_vector(1 downto 0);
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signal tabc : std_logic_vector(2 downto 0);
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begin
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with tabc select oper <=
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                          '0' & Ai + Bi  when "001",
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                          '0' & Ai + Bi when "010" ,
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                          '0' & Ai - '1' when "011" ,
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                    '0' & Ai + '1' when "100" ,
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                          '0' & Ai - Bi when "101" ,
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                          '0' & Ai + Bi + '1' when "110",
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                          '0' & Ai when others;
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Co <= oper(1);
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Go <= oper(0);
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tabc <= Ci&S;
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end architecture;

II) The structural code to link 4 cells to implement the arithmetic 
operator
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library ieee;
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use ieee.std_logic_1164.all,ieee.std_logic_unsigned.all;
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entity operator is
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port(A,B : in std_logic_vector(3 downto 0);
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     S : in std_logic_vector(1 downto 0);
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     cin : in std_logic;
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     G : out std_logic_vector(3 downto 0);
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     cout : out std_logic);
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end entity;
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architecture rtl of operator is
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component cell is 
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port(Ai,Bi,Ci : in std_logic;
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     S : in std_logic_vector (1 downto 0);
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     Co,Go : out std_logic);
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end component;
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signal C : std_logic_vector(3 downto 1);
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begin
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cell0 : cell port map(Ai=>A(0),Bi=>B(0),Ci=>cin,S=>S,Co =>C(1),Go => G(0));
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cell1 : cell port map(Ai=>A(1),Bi=>B(1),Ci=>C(1),S=>S,Co=>C(2),Go => G(1));
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cell2 : cell port map(Ai=>A(2),Bi=>B(2),Ci=>C(2),S=>S,Co=>C(3),Go => G(2));
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cell3 : cell port map(Ai=>A(3),Bi=>B(3),Ci=>C(3),S=>S,Co =>cout,Go =>G(3));
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end architecture;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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YouseKalack wrote:
> the result of the sub operation is not the result expected.
What do you expect and wht do you get instead?

> My code
Pls use the [vhdl] tags further on to wrap your code!
See the "Formatting options" above each edit box...

> use ieee.std_logic_unsigned.all;
> use ieee.numeric_std.all;
Never ever both together!
Otherwise you will encounter strange problems due to multiple type 
definitions.

: Edited by Moderator
von YouseKalack (Guest)


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The result expect would be "8" when S = "11" but the result is "2" as 
you can see in the simulation ....

von Yousekalack (Guest)


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My code :

I) The dataflow code to describe cell.
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.std_logic_unsigned.all;
4
use ieee.numeric_std.all;
5
6
entity cell is 
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port(Ai,Bi,Ci : in std_logic;
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     S : in std_logic_vector (1 downto 0);
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     Co,Go : out std_logic);
10
end cell;
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architecture dflow of cell is
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signal oper : std_logic_vector(1 downto 0);
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signal tabc : std_logic_vector(2 downto 0);
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begin
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with tabc select oper <=
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                          '0' & Ai + Bi  when "001",
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                          '0' & Ai + Bi when "010" ,
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                          '0' & Ai - '1' when "011" ,
20
                    '0' & Ai + '1' when "100" ,
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                          '0' & Ai - Bi when "101" ,
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                          '0' & Ai + Bi + '1' when "110",
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                          '0' & Ai when others;
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Co <= oper(1);
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Go <= oper(0);
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tabc <= Ci&S;
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end architecture;
II) The structural code to link 4 cells to implement the arithmetic
operator
1
library ieee;
2
use ieee.std_logic_1164.all,ieee.std_logic_unsigned.all;
3
4
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entity operator is
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port(A,B : in std_logic_vector(3 downto 0);
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     S : in std_logic_vector(1 downto 0);
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     cin : in std_logic;
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     G : out std_logic_vector(3 downto 0);
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     cout : out std_logic);
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end entity;
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architecture rtl of operator is
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component cell is 
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port(Ai,Bi,Ci : in std_logic;
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     S : in std_logic_vector (1 downto 0);
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     Co,Go : out std_logic);
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end component;
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signal C : std_logic_vector(3 downto 1);
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begin
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cell0 : cell port map(Ai=>A(0),Bi=>B(0),Ci=>cin,S=>S,Co =>C(1),Go => G(0));
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cell1 : cell port map(Ai=>A(1),Bi=>B(1),Ci=>C(1),S=>S,Co=>C(2),Go => G(1));
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cell2 : cell port map(Ai=>A(2),Bi=>B(2),Ci=>C(2),S=>S,Co=>C(3),Go => G(2));
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cell3 : cell port map(Ai=>A(3),Bi=>B(3),Ci=>C(3),S=>S,Co =>cout,Go =>G(3));
25
end architecture;

von Lothar M. (lkmiller) (Moderator)


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YouseKalack wrote:
> as you can see in the simulation ....
So setup a second test bench for your "cell" and have a look wether its 
working as desired.

> I) The dataflow code to describe cell.
By looking at the picture bottom left corner a thought pops up in my 
mind: shouldn't that "cell" also be described as a logic/structural 
expression instead as a functional data flow description? And shouldn't 
the CI be used for any operation in the "cell"?

To clear the view: the top left hand table is not related to the "cell" 
driectly. That table shows the expected behaviour of the top level 
module "operator".

: Edited by Moderator
von Achim S. (Guest)


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in your description of "cell" you never set the Carry-output. Oper(1) is 
set to 0 for all possible combinations of input signals. Your arithmetic 
won't work without correct Carry-Signals.

von Yousekalack (Guest)


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Yes the test work for one cell but only sub is not working good.. i 
think the problem is when A = '0' and A - 1 = ???

von Achim S. (Guest)


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Yousekalack wrote:
> Yes the test work for one cell but only sub is not working good.. i
> think the problem is when A = '0' and A - 1 = ???

No, for a single cell your code is also not working correctly.

Perform a simulation for a single cell. What are the correct outputs for 
A=0, Cin=0 and opeartion A-1? What does your simulation show instead?

von Huynh J. (yousekalack)


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This is the test for one cell with Ai = 0, Ci = 0 and S = '11'

von Huynh J. (yousekalack)


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Oper(1) is the carry out from all operations, i put'0' & but the '0' 
will be replace if there is a carry

von Achim S. (Guest)


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Huynh J. wrote:
> Oper(1) is the carry out from all operations, i put'0' & but the '0'
> will be replace if there is a carry

ok you're right, my mistake. "&" and "-" have identical priority and are 
evaluted from left to right. So

   '0' & Ai - '1'

turns into

  ('0' & Ai) - '1'

and then  the higer bit (i.e. the carry) can indeed be set after the 
operation

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