# Forum: FPGA, VHDL & Verilog Vhdl clockdivider

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Design a Clock divider that divides clock to 2,4,8,16 according to
binary input of x i.e.x equals “00”,”01”,”10”,”11”.assume that you have
100 mhz clock frequency

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Stupid, see
https://www.codeproject.com/Tips/444385/Frequency-Divider-with-VHDL-2
und use your brain.

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S. Lee Cooper wrote:
> Stupid, see
> https://www.codeproject.com/Tips/444385/Frequency-Divider-with-VHDL-2
> und use your brain.

You are soo rude i dont know this section and i try to learn But thank
your help ?

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Kadir A. wrote:
> Design a Clock divider that divides clock to 2,4,8,16 according to
> binary input of x i.e.x equals “00”,”01”,”10”,”11”.

> assume that you have 100 mhz clock frequency
Thats unnecessary, redundant information. A clock divider will divide
10kHz with the same technique as it does with 100MHz.

> mhz
milli Hertz?

> You are soo rude
Welcome in real life. Did you check out the information provided in the
link? I find it useful.

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Kadir A. wrote:
> You are soo rude i dont know this section and i try to learn But thank
> your help ?

Even though I find rude words unnecessary, you just posted something
that looks like a homework question, badly formatted, without any input
or suggestions from yourself and then you complained after someone
provided you information.

Don't expect people to put work into your problem if you don't show
effort yourself first, especially if you ask people on the internet and
Good luck to you.