Hi there, I'm embarking on a project to develop a measurement system, as well as basic FPGA configuration skills. It was new to me 4 weeks ago, but I'm beginning to pick up the intuition. My overarching goal is -to collect a N-sample length of data -perform some digital processing on that data -store a final value -repeat and average Currently, I am deciding how I will collect each set of N samples from an on board 16-bit ADC. I get 5 samples at a time, and I would like to accumulate them into an array so I can easily index into it for mean-subtraction/demodulation/FIR-filtering purposes. I have been reading about in-chip RAM, on board SRAM, and also the concept of FIFO devices. Would a FIFO module be able to buffer N=1000+ samples into a single array? I was beginning to write something using unpacked SystemVerilog arrays, but I had a feeling that they would not synthesize into something pretty or optimal. Is there a standard way to approach this, Advanced Thanks!
Aron L. wrote: > Is there a standard way to approach this If possible: use the RAM blocks inside the FPGA. They're big enough and its by far the most easy way. > to buffer N=1000+ samples into a single array Make the buffer size a power of 2 eg. 1024, 2048..., then handling of the fifo pointers is incredibly simple. > they would not synthesize into something pretty or optimal. Read the synthesizer manual how to describe the RAM to get it fit into the RAM blocks. Otherwise you will get some strange kind of memory. In the worst case the synthesizer must spend a lot of function blocks with their flipflops for storing.
Hi, I think the optimal solution depends on the sample rate. If high then you need to implement it in HDL if lower I would go for an embedded RISC-V MCU like Instant SoC (http://www.fpga-cores.com/instant-soc/) or something similar. AXI4 streams is very nice to work with when doing DSP stuff. Instant SoC supports AXI4 stream very good.
: Edited by User
Thanks, both of these suggestions are extremely helpful. I will return to this thread if my I encounter issues following these pathways.