EmbDev.net

Forum: FPGA, VHDL & Verilog clocking module in vivado?


von Flat B. (flatbyte)


Rate this post
0 useful
not useful
Hi,

Quite often I see such piece of code on the github repositories. I 
wonder how such code is generated in vivado - i mean, is there any 
ready-to-use graphical library that generates such code? Many projects 
contains only vhdl files (without any blocks design).

It looks like a template that was generated by some tool or library.

example below:
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
4
library UNISIM;
5
use UNISIM.VComponents.all;
6
7
entity clocking is
8
    Port ( clk100MHz : in STD_LOGIC;
9
           clk125MHz : out STD_LOGIC;
10
           clk125MHz90 : out STD_LOGIC);
11
end clocking;
12
13
architecture Behavioral of clocking is
14
    signal clk100MHz_buffered     : std_logic := '0';
15
    signal clkfb                  : std_logic := '0';
16
    signal clk125MHz_unbuffered   : STD_LOGIC;
17
    signal clk125MHz90_unbuffered : STD_LOGIC;
18
begin
19
bufg_100: BUFG 
20
    port map (
21
        i => clk100MHz,
22
        o => clk100MHz_buffered
23
    );
24
   -------------------------------------------------------
25
   -- Generate a 125MHz clock from the 100MHz 
26
   -- system clock 
27
   ------------------------------------------------------- 
28
pll_clocking : PLLE2_BASE
29
   generic map (
30
      BANDWIDTH          => "OPTIMIZED",
31
      CLKFBOUT_MULT      => 10,
32
      CLKFBOUT_PHASE     => 0.0,
33
      CLKIN1_PERIOD      => 10.0,
34
35
      -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
36
      CLKOUT0_DIVIDE     => 8,  CLKOUT1_DIVIDE     => 20, CLKOUT2_DIVIDE      => 40, 
37
      CLKOUT3_DIVIDE     => 8,  CLKOUT4_DIVIDE     => 16, CLKOUT5_DIVIDE      => 16,
38
39
      -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
40
      CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5,
41
      CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5,
42
43
      -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
44
      CLKOUT0_PHASE      =>    0.0, CLKOUT1_PHASE      => 0.0, CLKOUT2_PHASE      => 0.0,
45
      CLKOUT3_PHASE      => -270.0, CLKOUT4_PHASE      => 0.0, CLKOUT5_PHASE      => 0.0,
46
47
      DIVCLK_DIVIDE      => 1,
48
      REF_JITTER1        => 0.0,
49
      STARTUP_WAIT       => "FALSE"
50
   )
51
   port map (
52
      CLKIN1   => CLK100MHz_buffered,
53
      CLKOUT0  => CLK125MHz_unbuffered,   CLKOUT1 => open,  CLKOUT2 => open,  
54
      CLKOUT3  => CLK125MHz90_unbuffered, CLKOUT4 => open,  CLKOUT5 => open,
55
      LOCKED   => open,
56
      PWRDWN   => '0', 
57
      RST      => '0',
58
      CLKFBOUT => clkfb,
59
      CLKFBIN  => clkfb
60
   );
61
62
bufg_125Mhz: BUFG 
63
    port map (
64
        i => clk125MHz_unbuffered,
65
        o => clk125MHz
66
    );
67
68
bufg_125Mhz90: BUFG 
69
    port map (
70
        i => clk125MHz90_unbuffered,
71
        o => clk125MHz90
72
    );
73
74
end Behavioral;

Many thanks

von one of the Yes men (Guest)


Rate this post
1 useful
not useful
Flat B. wrote:

> wonder how such code is generated in vivado - i mean, is there any
> ready-to-use graphical library that generates such code?
Yes, there is, See vivado manuals for "Code generator"

https://www.xilinx.com/support/documentation/university/ISE-Teaching/HDL-Design/14x/Nexys3/Verilog/docs-pdf/lab8.pdf

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.