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clocking module in vivado?
von Flat B. (flatbyte)

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Hi,

Quite often I see such piece of code on the github repositories. I 
wonder how such code is generated in vivado - i mean, is there any 
ready-to-use graphical library that generates such code? Many projects 
contains only vhdl files (without any blocks design).

It looks like a template that was generated by some tool or library.

example below:

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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library UNISIM;

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use UNISIM.VComponents.all;

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entity clocking is

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    Port ( clk100MHz : in STD_LOGIC;

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           clk125MHz : out STD_LOGIC;

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           clk125MHz90 : out STD_LOGIC);

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end clocking;

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architecture Behavioral of clocking is

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    signal clk100MHz_buffered     : std_logic := '0';

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    signal clkfb                  : std_logic := '0';

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    signal clk125MHz_unbuffered   : STD_LOGIC;

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    signal clk125MHz90_unbuffered : STD_LOGIC;

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begin

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bufg_100: BUFG 

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    port map (

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        i => clk100MHz,

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        o => clk100MHz_buffered

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    );

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   -------------------------------------------------------

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   -- Generate a 125MHz clock from the 100MHz 

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   -- system clock 

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   ------------------------------------------------------- 

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pll_clocking : PLLE2_BASE

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   generic map (

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      BANDWIDTH          => "OPTIMIZED",

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      CLKFBOUT_MULT      => 10,

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      CLKFBOUT_PHASE     => 0.0,

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      CLKIN1_PERIOD      => 10.0,

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      -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)

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      CLKOUT0_DIVIDE     => 8,  CLKOUT1_DIVIDE     => 20, CLKOUT2_DIVIDE      => 40, 

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      CLKOUT3_DIVIDE     => 8,  CLKOUT4_DIVIDE     => 16, CLKOUT5_DIVIDE      => 16,

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      -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).

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      CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5,

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      CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5,

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      -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).

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      CLKOUT0_PHASE      =>    0.0, CLKOUT1_PHASE      => 0.0, CLKOUT2_PHASE      => 0.0,

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      CLKOUT3_PHASE      => -270.0, CLKOUT4_PHASE      => 0.0, CLKOUT5_PHASE      => 0.0,

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      DIVCLK_DIVIDE      => 1,

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      REF_JITTER1        => 0.0,

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      STARTUP_WAIT       => "FALSE"

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   )

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   port map (

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      CLKIN1   => CLK100MHz_buffered,

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      CLKOUT0  => CLK125MHz_unbuffered,   CLKOUT1 => open,  CLKOUT2 => open,  

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      CLKOUT3  => CLK125MHz90_unbuffered, CLKOUT4 => open,  CLKOUT5 => open,

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      LOCKED   => open,

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      PWRDWN   => '0', 

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      RST      => '0',

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      CLKFBOUT => clkfb,

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      CLKFBIN  => clkfb

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   );

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bufg_125Mhz: BUFG 

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    port map (

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        i => clk125MHz_unbuffered,

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        o => clk125MHz

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    );

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bufg_125Mhz90: BUFG 

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    port map (

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        i => clk125MHz90_unbuffered,

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        o => clk125MHz90

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    );

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end Behavioral;


Many thanks

  


  




  

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    Re: clocking module in vivado?
  


  

    

      von
      
        one of the Yes men (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Flat B. wrote:

> wonder how such code is generated in vivado - i mean, is there any
> ready-to-use graphical library that generates such code?
Yes, there is, See vivado manuals for "Code generator"

https://www.xilinx.com/support/documentation/university/ISE-Teaching/HDL-Design/14x/Nexys3/Verilog/docs-pdf/lab8.pdf

  


  




  

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