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Forum: FPGA, VHDL & Verilog Write in a file with verilog


Write in a file with verilog
von XaBla (Guest)

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Hello, I'd like to write a value in a file. This is the code I have 
implemented:

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task speed;

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    input [23:0] v;

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    input [23:0] s;

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    integer f;

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      begin

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          f = $fopen("test.txt","w");

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              if (!f) begin

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                $display("Could not open \"test.txt\"");

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              end else begin

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              #70000;

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                for(int i=0; i<24; i++) begin

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                  $fwrite(f,"%b", s[i]);

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                end

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              end

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              #10000

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          $fclose(f);  

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     end

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  endtask

Unfortunately, what I read is "xxxxxxxxxxxxxxxxxxxxxxxx". I was thinking 
that this happens since the date is not available when I try to write 
it, so I put a delay, but it's not still working. Can anyone help me 
please?

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Re: Write in a file with verilog
von Vancouver (Guest)

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Put $display() inside the for loop to check if input data is defined 
while writing to the file. Not sure if the delay in your code has any 
effect if the input data is undefined at the point when the task is 
called. Remember that a task is a pure software function that is 
executed by the simulator at the time when it is called, not permanently 
like an 'always' construct.

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Re: Write in a file with verilog
von Duke Scarring (Guest)

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XaBla wrote:
> Unfortunately, what I read is "xxxxxxxxxxxxxxxxxxxxxxxx".
I think the problem is not in the code you have showed us.
Also long as your  "input [23:0] s" is undefined you will get the 'x'es.

Duke

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