library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity simple_sine_gen is

    port

    (

        clk     : in  std_ulogic;

        --

        sine    : out signed( 7 downto 0)

    );

end entity simple_sine_gen;

architecture rtl of simple_sine_gen is

    constant amplitude  : natural   := 15; -- max. 15

    constant frequency  : natural   :=  1; -- 1..16(?)

    --

    constant value      : natural   := 512;

    type reg_t is record

        x   : signed( 15 downto 0);

        xt  : signed( 15 downto 0);

        xa  : signed( 15 downto 0);

        y   : signed( 15 downto 0);

        yt  : signed( 15 downto 0);

        ya  : signed( 15 downto 0);

    end record;

    constant default_reg_c : reg_t := 

    (

        x   => to_signed(                 0, 16),

        xt  => ( others => '0'),

        xa  => ( others => '0'),

        y   => to_signed( amplitude * value, 16),

        yt  => ( others => '0'),

        ya  => ( others => '0')

    );

    signal r    : reg_t := default_reg_c;

    signal r_in : reg_t := default_reg_c;

begin

    comb: process( r)

        variable v : reg_t;

    begin

        v   := r;

        -- output

        sine <= resize( shift_right( v.x, 6), 8);

        -- calculation

        v.xa    := v.x + v.xt;

        v.xt    := resize( frequency * v.ya / value, 16);

        v.x     := v.x + v.xt; 

        v.ya    := v.y - v.yt;

        v.yt    := resize( frequency * v.xa / value, 16);

        v.y     := v.y - v.yt;

        r_in <= v;

    end process;

    seq : process

    begin

        wait until rising_edge(clk);

        r <= r_in;

    end process;

end architecture rtl;