Forum: FPGA, VHDL & Verilog sine wave in vhdl

 Author: Sheikh S. (Company: sheikh) (sheikh) Posted on: 2019-06-11 15:50

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I want to generate sine wave in vhdl

 Author: lachs01 (Guest) Posted on: 2019-06-11 15:55

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so do it.

 Author: Duke Scarring (Guest) Posted on: 2019-06-11 16:30

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 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity simple_sine_gen is port ( clk : in std_ulogic; -- sine : out signed( 7 downto 0) ); end entity simple_sine_gen; architecture rtl of simple_sine_gen is constant amplitude : natural := 15; -- max. 15 constant frequency : natural := 1; -- 1..16(?) -- constant value : natural := 512; type reg_t is record x : signed( 15 downto 0); xt : signed( 15 downto 0); xa : signed( 15 downto 0); y : signed( 15 downto 0); yt : signed( 15 downto 0); ya : signed( 15 downto 0); end record; constant default_reg_c : reg_t := ( x => to_signed( 0, 16), xt => ( others => '0'), xa => ( others => '0'), y => to_signed( amplitude * value, 16), yt => ( others => '0'), ya => ( others => '0') ); signal r : reg_t := default_reg_c; signal r_in : reg_t := default_reg_c; begin comb: process( r) variable v : reg_t; begin v := r; -- output sine <= resize( shift_right( v.x, 6), 8); -- calculation v.xa := v.x + v.xt; v.xt := resize( frequency * v.ya / value, 16); v.x := v.x + v.xt; v.ya := v.y - v.yt; v.yt := resize( frequency * v.xa / value, 16); v.y := v.y - v.yt; r_in <= v; end process; seq : process begin wait until rising_edge(clk); r <= r_in; end process; end architecture rtl;

Can you explain how it works?

 Author: Sheikh's Electronics Teacher (Guest) Posted on: 2019-07-13 23:14

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Thanks to Duke, you now know about the way to realise 2 stage diff
equations in VHDL. Anyway you should have been able to figure that out
yourself.

 Author: Lothar M. (lkmiller) (Moderator) Posted on: 2019-07-13 23:46

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Sheikh S. wrote:
> I want to generate sine wave in vhdl
And what's the problem? How far did you get? How can we help?

 Author: Gerhard H. (ghf) Posted on: 2019-08-07 21:20

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https://opencores.org/projects/sincos

you can reach the author here.  :-)

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