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register clear on read
von vhdl (Guest)

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I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers 
clear on read which counts the number of words in error and the number 
of bits in error. i want to know how  i can code a register clear on 
read in vhdl?
thank you,

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Re: register clear on read
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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vhdl wrote:
> I have to put 2 registers clear on read
Usually thats a really bad (better: a stupid) idea in real life. Because 
you will encounter strange behavior when this "automatic reset register" 
ist used in a processor system. Because then it may be that debugger is 
told to show some values around this register and it reads this register 
additionally into a cache for "future use". But by reading the register 
its reset to 0 --> weird behavior of your software.

> i want to know how  i can code a register clear on read in vhdl?
You must reset the register somewhere near to the line where it cpounts 
up.

The final implementaion depends heavily on what you already have...

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Re: register clear on read
von Vancouver (Guest)

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Atomic read&clear operations on registers are quite common in signal 
processing. If you need to count the exact number of events (e.g. 
uncorrectable bit errors in a Reed Solomon Decoder) over a certain time 
interval, usually a counting register is used which is cleared upon 
read. If reading and clearing were non-atomic, there may occur further 
events in between that are never counted.

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Re: register clear on read
von Sigi (Guest)

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This technique can be found in many Devices.
(e.g. in the old C64, the MOS6522 and 6526 use
this for interrupt bits)

Together with a CPU and a simple Bus System, it can be
implemented like this:

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-- ce  : chip enable

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-- we  : write enable

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-- addr: bus address

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-- do  : bus data output

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if rising_edge(clk) then -- clocking

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  case addr is

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    ..

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    when REG1 => do <= reg1value;

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                 if ce = '1' and we = '0' then

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                   reg1value <= (others => '0');

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                 end if;

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    when REG2 => do <= reg1value;

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                 reg2value <= (others => '0');

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                 if ce = '1' and we = '0' then

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                   reg2value <= (others => '0');

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                 end if;

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    ..

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  end case;

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end if; -- clocking


  


  




  

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