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Forum: FPGA, VHDL & Verilog register clear on read


Author: vhdl (Guest)
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I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers 
clear on read which counts the number of words in error and the number 
of bits in error. i want to know how  i can code a register clear on 
read in vhdl?
thank you,

Author: Lothar M. (lkmiller) (Moderator)
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vhdl wrote:
> I have to put 2 registers clear on read
Usually thats a really bad (better: a stupid) idea in real life. Because 
you will encounter strange behavior when this "automatic reset register" 
ist used in a processor system. Because then it may be that debugger is 
told to show some values around this register and it reads this register 
additionally into a cache for "future use". But by reading the register 
its reset to 0 --> weird behavior of your software.

> i want to know how  i can code a register clear on read in vhdl?
You must reset the register somewhere near to the line where it cpounts 
up.

The final implementaion depends heavily on what you already have...

Author: Vancouver (Guest)
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Atomic read&clear operations on registers are quite common in signal 
processing. If you need to count the exact number of events (e.g. 
uncorrectable bit errors in a Reed Solomon Decoder) over a certain time 
interval, usually a counting register is used which is cleared upon 
read. If reading and clearing were non-atomic, there may occur further 
events in between that are never counted.

Author: Sigi (Guest)
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This technique can be found in many Devices.
(e.g. in the old C64, the MOS6522 and 6526 use
this for interrupt bits)

Together with a CPU and a simple Bus System, it can be
implemented like this:

-- ce  : chip enable
-- we  : write enable
-- addr: bus address
-- do  : bus data output

if rising_edge(clk) then -- clocking

  case addr is
    ..
    when REG1 => do <= reg1value;
                 if ce = '1' and we = '0' then
                   reg1value <= (others => '0');
                 end if;
    when REG2 => do <= reg1value;
                 reg2value <= (others => '0');
                 if ce = '1' and we = '0' then
                   reg2value <= (others => '0');
                 end if;
    ..
  end case;

end if; -- clocking

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