I'm designing a PWM module,with a 4 bits control.
My specs,a 4-bits input control,input clock 50MHz,
a single bit output PWM_o,
when control changes,the duty cycle of PWM_o changes,
like control = 0,PWM_o = 0;Control = 1,PWM_o = 6.25%...increase 6.25%
each time(meaning that PWM_o should be wider and wider each time it
outputs when Control increase).Desired result should be like marked with
red rectangular in the first photo.
I've tried so many version of ways to write it,I've noticed the common
issue is that my Control changing too fast and I don't know how to delay
it,I need to make the Control change after 16 pulses of input Clock,I
just can't figure out how to do it...
I don't understand how to delay a set of multiple bits of input...
Here down below are my attempting,my attempting's output is almost
correct,but just the issue with the Control..
Noted: Control is named as `value` in the codes;
Hallo wrote:> Try to register value when the counter runs over and compare (attemp 3)
But the `value` is an `input`,I don't think that the `input` can be
declared as a register.Or perhaps you can enlighten me...
although,I still tried to use D-Flip Flops to delay the `input`
,but the result came out wrong...and error.
My DFF attempting looks like this:
So far,using DFF is the only way I could think of to delay the
input...But it came out nothing...
>the registered value with counter.
Do you mean compare the registered value with counter?
It's also hard to say what really should happen since value changes more
frequently than the counter run over. What should happen when value
changes from 0 to 3 and then stay stable for 4*16 clock cycles?
>> Code not tested, is also not complete solution but should point into> right direction...
I know your idea and I thought about this as well and used a 8bits
counter to delay as well,but the problem remain...it won't actually
delay the input value,instead it make the counter stop at the value...
else if(counter == 8'd15)
counter <= counter + 8'd1;
I even tried the much more simpler way to express the PWM_out result,but
the input value issue still remain...it still changing too fast,it won't
wait till 16 pulses of clock before change...
Hallo wrote:> It's also hard to say what really should happen since value changes more> frequently than the counter run over. What should happen when value> changes from 0 to 3 and then stay stable for 4*16 clock cycles?
No,The first attachment is what I'm trying to show,that the each value
should wait for 16 clock cycles before going to the next,like;
value = 0 and PWM_out = 0 and equal to 16 clock cycles then value
changes to 1,PWM_out= almost 1 clock cycle and equal to 16 clock cycles
then value changes to 2,PWM_out = 1 clock cycle...etc...
Maybe I'll put it in this way,each `value` is equal to 16 clock cycles.
PWM_out only output at counter==15,and value's 16 clock cycle.
I've redraw the photo...maybe you'll be much more clearly.
But noted,by continue to repeat,I meant that to when value changes to 4
...PWM_out output equal to 4 clock cycles and value is equal to 16 clock
cycles. I don't mean 0-1-2-3 to continue repeat but rather the clock
Your new drawing and my proposal should fit very well
If you would like to have every change of value been "processed", even
value changes more often than the counter runs over you need an FIFO and
push data in if value change and pull data out when the counter runs
Hallo wrote:> Your new drawing and my proposal should fit very well>> If you would like to have every change of value been "processed", even> value changes more often than the counter runs over you need an FIFO and> push data in if value change and pull data out when the counter runs> over.
If your proposal will do what I wanted,
But I only see data in in your proposal,How can I pull it out? I might
need more hint,'cause I'm really stuck.
reg [3:0] value_dly;
always_ff@(posedge clk) begin
end else if (counter == 4'hf) begin
value_dly <= value;
//Here suppose to have a else begin counter <= counter + 4'h1; end , right?
Hallo wrote:> You change value with every clock cycle.> Change of value must be proper specified and I just assumed now that it> is only allowed to change when the counter runs over.
Ok,I finally understood it,the change of value is what I should set it
when I simulate it...and 16 clock cycles is what I should count and then
set the value...
So...It was never the code's problem...
I've got stuck at this for days...THANK YOU SO MUCH.