Digital clock 7-seg display NEXYS-3

peterkraft Guest #5850883
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Hi,
I have to do a project in VHDL on NEXYS3 Spartan6 FPGA board.
I tried many things but nothing actually worked for me. Could anyone 
possibly help me and write the code how to make a digital clock based on 
7 segment display?
It should display hours and minutes, contain 2 switches to increment 
hours and minutes and have a diode ticking every seconds.
Id like to see as primitive code as its possible to understand easily.
Thanks for help
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Lothar M. Moderator (Company: Titel) #5850945
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peterkraft wrote:
> help me and write the code
Whoms homework is this?
Why don't you start with something and when you encounter a specific 
problem then you ask for a hint.

> have a diode ticking every seconds.
Start with this task. Give your own try two evenings. At least...

Afterwards there's a super simple solution for a stop watch:
http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html
It's fairly easy to understand and adapt to your job. Try Google 
translate, it's German.
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peterkraft Guest #5851235
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1
library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_arith.all;

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use ieee.std_logic_unsigned.all;

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entity clockdigit is

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port (clk1 : in std_logic;

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      seconds : out std_logic_vector(5 downto 0);

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      minutes : out std_logic_vector(5 downto 0);

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      hours : out std_logic_vector(2 downto 0)

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     );

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end clockdigit ;

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architecture Behavioral of clockdigit  is

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signal sec,min,hour : integer range 0 to 60;

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signal count : integer :=1;

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signal clk : std_logic :='0';

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begin

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process(clk1)

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begin

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if(clk1'event and clk1='1') then

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count <=count+1;

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if(count = 50000000) then

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clk <= not clk;

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count <=1;

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end if;

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end if;

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end process;

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process(clk)

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begin

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if(clk'event and clk='1') then

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sec <= sec+ 1;

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if(sec = 59) then

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sec<=0;

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min <= min + 1;

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if(min = 59) then

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hour <= hour + 1;

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min <= 0;

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if(hour = 23) then

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hour <= 0;

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end if;

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end if;

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end if;

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end if;

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end process;

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end Behavioral;





I've done something like this, but I still dont know how to display it 
on 7-seg display. Id like to display hours and minutes, and make a 
ticking diode every second. Could you possibly help with the code?
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Lothar M. Moderator (Company: Titel) #5851262
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peterkraft wrote:
> I've done something like this
It is NOT a proper way to generate clocks inside a FPGA. You will get a 
warning for such a design style. Use clock-enable signals for that.

> if(count = 50000000) then
This is the well known "off-by-one" error. Not much of a problem here, 
because it will get only 1/50000000 deviation for your clock. That means 
your clock will be off by one second after almost a year due to that 
error. But when you would do that to count milliseconds, then the 
deviation would be a quarter of an hour...

> Could you possibly help with the code?
Did you click on that link?
There you can see 1. how to use the numeric_std package and 2. how to 
use clock enables and 3. how to get the digits to the display and 4. 
that it is much better to count each of the 4 digits by its own, so it 
can easily be displayed. Because with your code you encounter the 
problem to fiddle the 4 digits out the hours and miuntes.

BTW:
> I've done something like this
Pls use the [vhdl] tags to wrap your code.
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C. A. Rotwang Guest #5851278
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write your code more readable:

>
1
process(clk)

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begin

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 if rising_edge(clk) then

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--add 'tick every second' condition here

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  if sec = 59 then

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   sec <= 0;

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  else

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   sec <= sec + 1;

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  end if;

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  if min = 59 then

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   min <= 0;

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  else

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   min <= min + 1;

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  end if;

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  if hour = 23 then

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   hour <= 0;

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  else

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   hour <= hour + 1;

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  end if;

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 --add closing end if of tick condition here 

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 end if;

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end process;
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