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Forum: FPGA, VHDL & Verilog Digital clock 7-seg display NEXYS-3


Author: peterkraft (Guest)
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Hi,
I have to do a project in VHDL on NEXYS3 Spartan6 FPGA board.
I tried many things but nothing actually worked for me. Could anyone 
possibly help me and write the code how to make a digital clock based on 
7 segment display?
It should display hours and minutes, contain 2 switches to increment 
hours and minutes and have a diode ticking every seconds.
Id like to see as primitive code as its possible to understand easily.
Thanks for help

Author: Lothar M. (lkmiller) (Moderator)
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peterkraft wrote:
> help me and write the code
Whoms homework is this?
Why don't you start with something and when you encounter a specific 
problem then you ask for a hint.

> have a diode ticking every seconds.
Start with this task. Give your own try two evenings. At least...

Afterwards there's a super simple solution for a stop watch:
http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html
It's fairly easy to understand and adapt to your job. Try Google 
translate, it's German.

Author: peterkraft (Guest)
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clockdigit is
port (clk1 : in std_logic;
      seconds : out std_logic_vector(5 downto 0);
      minutes : out std_logic_vector(5 downto 0);
      hours : out std_logic_vector(2 downto 0)
     );
end clockdigit ;

architecture Behavioral of clockdigit  is
signal sec,min,hour : integer range 0 to 60;
signal count : integer :=1;
signal clk : std_logic :='0';
begin


process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;

process(clk)
begin

if(clk'event and clk='1') then
sec <= sec+ 1;
if(sec = 59) then
sec<=0;
min <= min + 1;
if(min = 59) then
hour <= hour + 1;
min <= 0;
if(hour = 23) then
hour <= 0;
end if;
end if;
end if;
end if;

end process;

end Behavioral;




I've done something like this, but I still dont know how to display it 
on 7-seg display. Id like to display hours and minutes, and make a 
ticking diode every second. Could you possibly help with the code?

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
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peterkraft wrote:
> I've done something like this
It is NOT a proper way to generate clocks inside a FPGA. You will get a 
warning for such a design style. Use clock-enable signals for that.

> if(count = 50000000) then
This is the well known "off-by-one" error. Not much of a problem here, 
because it will get only 1/50000000 deviation for your clock. That means 
your clock will be off by one second after almost a year due to that 
error. But when you would do that to count milliseconds, then the 
deviation would be a quarter of an hour...

> Could you possibly help with the code?
Did you click on that link?
There you can see 1. how to use the numeric_std package and 2. how to 
use clock enables and 3. how to get the digits to the display and 4. 
that it is much better to count each of the 4 digits by its own, so it 
can easily be displayed. Because with your code you encounter the 
problem to fiddle the 4 digits out the hours and miuntes.

BTW:
> I've done something like this
Pls use the [vhdl] tags to wrap your code.

: Edited by Moderator
Author: C. A. Rotwang (Guest)
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write your code more readable:

>
process(clk)
begin
 if rising_edge(clk) then
--add 'tick every second' condition here
  if sec = 59 then
   sec <= 0;
  else
   sec <= sec + 1;
  end if;

  if min = 59 then
   min <= 0;
  else
   min <= min + 1;
  end if;

  if hour = 23 then
   hour <= 0;
  else
   hour <= hour + 1;
  end if;
 --add closing end if of tick condition here 
 end if;
end process;

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