EmbDev.net

Forum: FPGA, VHDL & Verilog ws2812 vhdl problem


von Flat B. (flatbyte)


Attached files:

Rate this post
useful
not useful
Hi there,

I tried to run vhdl code from 
https://github.com/trobanga/ws2812/blob/master/ws2812.vhdl

The strange thing is that timings are not met. As described in code, i 
connect 50mhz clock to the ip block.
Can someone give me a hand with this and test vhdl code? Results 
attached.

Many thanks,
FlatByte

von Lothar M. (lkmiller) (Moderator)


Rate this post
useful
not useful
Flat B. wrote:
> i connect 50mhz
milli Hertz?

> The strange thing is that timings are not met.
As far as I see the timing is exactly as to be expected.
350ns are not possible with 20ns granularity, therefore the term g_T0H * 
CLOCK_FREQ / 1000 results in a time of 340ns. And the additional 40ns 
are due to the state transitions wh and wl in the FSM, so you must get 
340ns+20ns+800ns+20ns = 1180ns and 600ns+20ns+700ns+20ns = 1340ns with 
this code.

> The strange thing is that timings are not met.
What timing does a behavioural simulation show?

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


Attached files:

Rate this post
useful
not useful
I had 5 spare minutes, did a short behavioural simulation of that code 
and it looks like your measurement.

So that turns out the question: whats the actual problem?

: Edited by Moderator
von Flat B. (flatbyte)


Rate this post
useful
not useful
Wow, many thanks for the great discussion. At last I've found right 
place and right people for VHDL/FPGA discussion.

Lothar M. wrote:

> Flat B. wrote:
>
> > i connect 50mhz
> > milli Hertz?
Right. MHz.

Lothar M. wrote:

> The strange thing is that timings are not met.
> As far as I see the timing is exactly as to be expected.
> 350ns are not possible with 20ns granularity, therefore the term g_T0H *
> CLOCK_FREQ / 1000 results in a time of 340ns. And the additional 40ns
> are due to the state transitions wh and wl in the FSM, so you must get
> 340ns+20ns+800ns+20ns = 1180ns and 600ns+20ns+700ns+20ns = 1340ns with
> this code.
Wow. Thanks!

Lothar M. wrote:
> So that turns out the question: whats the actual problem?
As a "new" in VHDL/FPGA I was almost sure I did something wrong 
implementing ws2812.vhdl file. I expected 800khz for driving WS2812B 
leds.

Once again - many thanks! Your responses confirms that ws2812.vhdl 
doesn't generate 800 KHz pulse.


PS. ws2812.vhdl file is not mine - I've just found it on the internet.

von Lothar M. (lkmiller) (Moderator)


Attached files:

Rate this post
useful
not useful
Flat B. wrote:
> I expected 800khz for driving WS2812B leds.
According to the timing spec in the datasheet the solution is fine.
800kHz are onla a "typical" value. Its just the reciprocal value of the 
TH+TL=1.25μs, ignoring the ±600ns which results in 540kHz...1.5MHz.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.