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Forum: FPGA, VHDL & Verilog ws2812 vhdl problem


Author: Flat B. (flatbyte)
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Hi there,

I tried to run vhdl code from 
https://github.com/trobanga/ws2812/blob/master/ws2812.vhdl

The strange thing is that timings are not met. As described in code, i 
connect 50mhz clock to the ip block.
Can someone give me a hand with this and test vhdl code? Results 
attached.

Many thanks,
FlatByte

Author: Lothar M. (lkmiller) (Moderator)
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Flat B. wrote:
> i connect 50mhz
milli Hertz?

> The strange thing is that timings are not met.
As far as I see the timing is exactly as to be expected.
350ns are not possible with 20ns granularity, therefore the term g_T0H * 
CLOCK_FREQ / 1000 results in a time of 340ns. And the additional 40ns 
are due to the state transitions wh and wl in the FSM, so you must get 
340ns+20ns+800ns+20ns = 1180ns and 600ns+20ns+700ns+20ns = 1340ns with 
this code.

> The strange thing is that timings are not met.
What timing does a behavioural simulation show?

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
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I had 5 spare minutes, did a short behavioural simulation of that code 
and it looks like your measurement.

So that turns out the question: whats the actual problem?

: Edited by Moderator
Author: Flat B. (flatbyte)
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Wow, many thanks for the great discussion. At last I've found right 
place and right people for VHDL/FPGA discussion.

Lothar M. wrote:

> Flat B. wrote:
>
> > i connect 50mhz
> > milli Hertz?
Right. MHz.

Lothar M. wrote:

> The strange thing is that timings are not met.
> As far as I see the timing is exactly as to be expected.
> 350ns are not possible with 20ns granularity, therefore the term g_T0H *
> CLOCK_FREQ / 1000 results in a time of 340ns. And the additional 40ns
> are due to the state transitions wh and wl in the FSM, so you must get
> 340ns+20ns+800ns+20ns = 1180ns and 600ns+20ns+700ns+20ns = 1340ns with
> this code.
Wow. Thanks!

Lothar M. wrote:
> So that turns out the question: whats the actual problem?
As a "new" in VHDL/FPGA I was almost sure I did something wrong 
implementing ws2812.vhdl file. I expected 800khz for driving WS2812B 
leds.

Once again - many thanks! Your responses confirms that ws2812.vhdl 
doesn't generate 800 KHz pulse.


PS. ws2812.vhdl file is not mine - I've just found it on the internet.

Author: Lothar M. (lkmiller) (Moderator)
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Flat B. wrote:
> I expected 800khz for driving WS2812B leds.
According to the timing spec in the datasheet the solution is fine.
800kHz are onla a "typical" value. Its just the reciprocal value of the 
TH+TL=1.25μs, ignoring the ±600ns which results in 540kHz...1.5MHz.

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