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Forum: FPGA, VHDL & Verilog Variable clock with prescaler?


Author: Mohamed H. (Company: no) (mo7amed98)
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I wanted to make a vco to get 8 different values of frequencies 
dependent on controlfreq input and I made it successfully but for now I 
want to add another single bit input so when its value is '1' I divide 
each frequency of those by 1000 or in other words to get frequency by 
hertz instead of kilo hertz .. here's my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity VCO is
port (
controlfreq: in std_logic_vector(2 downto 0);
clock_out: out std_logic);
end VCO;

architecture bhv of VCO is
signal clk : std_logic;
signal div : std_logic_vector(7 downto 0):=(others=>'0');

begin

process(clk)
begin
if(clk'event and clk='1') then
div <= div + '1';
end if;
end process;

process(clk)
begin
if (controlfreq <= "000") then 
clock_out <= div(0);
elsif (controlfreq <= "001") then 
clock_out <= div(1);
elsif (controlfreq <= "010") then 
clock_out <= div(2);
elsif (controlfreq <= "011") then 
clock_out <= div(3);
elsif (controlfreq <= "100") then 
clock_out <= div(4);
elsif (controlfreq <= "101") then 
clock_out <= div(5);
elsif (controlfreq <= "110") then 
clock_out <= div(6);
elsif (controlfreq <= "111") then 
clock_out <= div(7);
end if;
end process;

end bhv;

: Edited by Moderator
Author: Duke Scarring (Guest)
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Mohamed H. wrote:
> want to add another single bit input so when its value is '1' I divide
> each frequency of those by 1000 or in other words to get frequency by
> hertz instead of kilo hertz .. here's my code
I don't see a real question (mark) here.
If you need other frequencies than you need another prescaler.

> use IEEE.STD_LOGIC_unsigned.ALL;
Don't use this, use ieee.numeric_std.all instead with all proper type 
definitions.

> if(clk'event and clk='1') then
rising_edge(clk) is more reader friendly (and has some small advantages 
in simulation).

> if (controlfreq <= "000") then
> clock_out <= div(0);
> elsif (controlfreq <= "001") then
> clock_out <= div(1);
> elsif (controlfreq <= "010") then
> clock_out <= div(2);
> elsif (controlfreq <= "011") then
> clock_out <= div(3);
> elsif (controlfreq <= "100") then
> clock_out <= div(4);
> elsif (controlfreq <= "101") then
> clock_out <= div(5);
> elsif (controlfreq <= "110") then
> clock_out <= div(6);
> elsif (controlfreq <= "111") then
> clock_out <= div(7);
I suggest to use the case-construct here. See:
https://en.wikibooks.org/wiki/Programmable_Logic/VHDL_Sequential_Statement
https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/Multiplexer

Duke

Author: Lothar M. (lkmiller) (Moderator)
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Mohamed H. wrote:
> for now I want to add another single bit input so when its value is '1'
> I divide each frequency of those by 1000
You will need an additional prescaler here:
signal prescaler : integer range 0 to 999 := 0;
:
:
  if(clk'event and clk='1') then
    if slowdown = '1' then  -- slowdown mode
        if prescaler = 999 then
           prescaler <= 0;
           div <= div + '1';
        else 
           prescaler <= prescaler+1;
        end if;           
    else                   -- traditional mode
        div <= div + '1';
    end if;
  end if;
:
:

Mohamed H. wrote:
> here's my code
Pls use the [vhdl] tags as described above every text input box.

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