Variable clock with prescaler?

Mohamed H. OP (Company: no) #5844195
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I wanted to make a vco to get 8 different values of frequencies 
dependent on controlfreq input and I made it successfully but for now I 
want to add another single bit input so when its value is '1' I divide 
each frequency of those by 1000 or in other words to get frequency by 
hertz instead of kilo hertz .. here's my code
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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_unsigned.ALL;

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entity VCO is

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port (

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controlfreq: in std_logic_vector(2 downto 0);

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clock_out: out std_logic);

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end VCO;

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architecture bhv of VCO is

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signal clk : std_logic;

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signal div : std_logic_vector(7 downto 0):=(others=>'0');

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begin

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process(clk)

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begin

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if(clk'event and clk='1') then

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div <= div + '1';

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end if;

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end process;

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process(clk)

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begin

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if (controlfreq <= "000") then 

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clock_out <= div(0);

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elsif (controlfreq <= "001") then 

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clock_out <= div(1);

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elsif (controlfreq <= "010") then 

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clock_out <= div(2);

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elsif (controlfreq <= "011") then 

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clock_out <= div(3);

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elsif (controlfreq <= "100") then 

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clock_out <= div(4);

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elsif (controlfreq <= "101") then 

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clock_out <= div(5);

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elsif (controlfreq <= "110") then 

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clock_out <= div(6);

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elsif (controlfreq <= "111") then 

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clock_out <= div(7);

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end if;

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end process;

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end bhv;
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Duke Scarring Guest #5845697
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Mohamed H. wrote:
> want to add another single bit input so when its value is '1' I divide
> each frequency of those by 1000 or in other words to get frequency by
> hertz instead of kilo hertz .. here's my code
I don't see a real question (mark) here.
If you need other frequencies than you need another prescaler.

> use IEEE.STD_LOGIC_unsigned.ALL;
Don't use this, use ieee.numeric_std.all instead with all proper type 
definitions.

> if(clk'event and clk='1') then
rising_edge(clk) is more reader friendly (and has some small advantages 
in simulation).

> if (controlfreq <= "000") then
> clock_out <= div(0);
> elsif (controlfreq <= "001") then
> clock_out <= div(1);
> elsif (controlfreq <= "010") then
> clock_out <= div(2);
> elsif (controlfreq <= "011") then
> clock_out <= div(3);
> elsif (controlfreq <= "100") then
> clock_out <= div(4);
> elsif (controlfreq <= "101") then
> clock_out <= div(5);
> elsif (controlfreq <= "110") then
> clock_out <= div(6);
> elsif (controlfreq <= "111") then
> clock_out <= div(7);
I suggest to use the case-construct here. See:
https://en.wikibooks.org/wiki/Programmable_Logic/VHDL_Sequential_Statement
https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/Multiplexer

Duke
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Lothar M. Moderator (Company: Titel) #5845717
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Mohamed H. wrote:
> for now I want to add another single bit input so when its value is '1'
> I divide each frequency of those by 1000
You will need an additional prescaler here:
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signal prescaler : integer range 0 to 999 := 0;

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:

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:

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  if(clk'event and clk='1') then

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    if slowdown = '1' then  -- slowdown mode

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        if prescaler = 999 then

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           prescaler <= 0;

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           div <= div + '1';

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        else 

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           prescaler <= prescaler+1;

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        end if;           

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    else                   -- traditional mode

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        div <= div + '1';

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    end if;

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  end if;

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:

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:


Mohamed H. wrote:
> here's my code
Pls use the [vhdl] tags as described above every text input box.
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