I wanted to make a vco to get 8 different values of frequencies
dependent on controlfreq input and I made it successfully but for now I
want to add another single bit input so when its value is '1' I divide
each frequency of those by 1000 or in other words to get frequency by
hertz instead of kilo hertz .. here's my code
1  library IEEE;

2  use IEEE.STD_LOGIC_1164.ALL;

3  use IEEE.STD_LOGIC_unsigned.ALL;

4  
5  entity VCO is

6  port (

7  controlfreq: in std_logic_vector(2 downto 0);

8  clock_out: out std_logic);

9  end VCO;

10  
11  architecture bhv of VCO is

12  signal clk : std_logic;

13  signal div : std_logic_vector(7 downto 0):=(others=>'0');

14  
15  begin

16  
17  process(clk)

18  begin

19  if(clk'event and clk='1') then

20  div <= div + '1';

21  end if;

22  end process;

23  
24  process(clk)

25  begin

26  if (controlfreq <= "000") then

27  clock_out <= div(0);

28  elsif (controlfreq <= "001") then

29  clock_out <= div(1);

30  elsif (controlfreq <= "010") then

31  clock_out <= div(2);

32  elsif (controlfreq <= "011") then

33  clock_out <= div(3);

34  elsif (controlfreq <= "100") then

35  clock_out <= div(4);

36  elsif (controlfreq <= "101") then

37  clock_out <= div(5);

38  elsif (controlfreq <= "110") then

39  clock_out <= div(6);

40  elsif (controlfreq <= "111") then

41  clock_out <= div(7);

42  end if;

43  end process;

44  
45  end bhv;
