hello everyone i try to increase the frequency of a VHDL code, I use Quartus to minimize the worst-case Timing Peths, i found that the worst is a block that calculates the minimum and à multiplexer. I Wonder if ther is a way to describe thoses block to increase the frequency without using the regesters. thank you . below the codes used:
a 2 to 1 multiplexer is the fastest you can describe, the comparator is also fast
abdelhak taamouch wrote: > i found that the worst is a block that calculates the minimum and à > multiplexer. Sounds like you are on the wrong path. This small code snippet itself is implemented fairly fast. So the question for absolute figures rises: what's the desired clock frequency? And what do you get?