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Forum: FPGA, VHDL & Verilog eye scan (eye diagram)


von kamal (Guest)


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hello all,

I want to make an eye scan(eye diagram) for the transceiver GTx of the 
family virtex 5, I want to know the possible approachs to achieve that.

thank you for your help

von Andreas (Guest)


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kamal wrote:
> I want to know the possible approachs to achieve that.

Whats your Lab equipment?

Kind regards,

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