How is it possible in vhdl to implement a control in a time window referred to a clock? For example, define a time window that starts 4 ns before the clock and ends 2 ns before the clock. Or a window that starts 2 ns before the clock and ends 1 ns after the clock. Or a window that starts 2 ns after the clock and ends 5 ns after the clock. Then determine if in this time window a data line has remained stable (no transitions). Regards
Luca M. wrote: > How is it possible in vhdl to implement a control in a time window > referred to a clock? Usually such measurements are done by a high speed oscilloscope... One way would be to implement a TDC (time to digital converter) and then compare the both inputs (clock and signal) to check the phase of those two signals. But given those tight timings (1 ns range) you must consider the input delay of a FPGA pad and later on the internal routing also. Because it may be that the timing at the pin is totally correct, but inside the FPGA there is a slack on the data line and at the actual flipflop it is delayed by 3ns. Here you must work with timing constraints on the signal line to be sure the routing is done properly. BTW: to control a signal is totally different than simply measure or to check a signal. Why do you need such a check?
Tnx Lothar. Sorry, i need check, not control. But i need only a simulation vhdl code for this. Not a Real misure with oscilloscope! I need simulate a flop with T setup and T hold. Case 1: tsetup and thold positive ( es 5ns, 1ns). Case 2 : setup positive and thold negative. Case 3: setup negative and hold positive. I need to check in this temporals windows if a data is stable. Vhdl code.
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Luca M. wrote: > How is it possible in vhdl to implement a control in a time window > referred to a clock? *Use google: https://www.google.com/search?q=check+setup+and+hold+in+VHDL&client=firefox-b-d&source=lnms&sa=X&ved=0ahUKEwj1zMjH86PgAhUC6KQKHcWNDQoQ_AUICSgA&biw=1280&bih=950&dpr=1 *Read i.e. this: http://www.oocities.org/siliconvalley/screen/2257/vhdl/tim_chk/tim_chk.html http://users.wpi.edu/~rjduck/Verilog%20for%20Modeling%20-%20module%209b.pdf *Say "Thank You".
Luca M. wrote: > I need to check in this temporals windows if a data is stable. Vhdl code. One question more: do you have to implement that in real hardware for real life signals or just simply for simulation? If the first: This cannot be done by "VHDL code" solely. You must have a very, very close look at the particular datasheet of your particular FPGA and figure out how you can implement a delay line for a TDC. If the second: Where does the input stimuli of your test bench come from? Do you perform a timing simulation? If so: why? I didn't do that since the last millenium. A proper synchronous design strategy together with proper timing constraints gets your design running easily. And all in all: Lothar M. wrote: > Why do you need such a check? And for what? Is it a real application or just homework?
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Edited by Moderator
There is no direct way to check. But you can write this checker with VHDL Attributes and Asserts: https://www.csee.umbc.edu/portal/help/VHDL/attribute.html
Example: SETUP_TIME: Time before the rising edge of clk where data must be stable HOLD_TIME: Time after the rising edge of clk where data must be stable Checker for Setup-Time:
1 | tsu_checker: process |
2 | begin
|
3 | wait until rising_edge(clk); |
4 | assert data'stable(SETUP_TIME) report "Setup violation!!" severity error; |
5 | end process; |
Checker for Hold-Time:
1 | thd_checker: process |
2 | begin
|
3 | wait until data'event; |
4 | if clk = '1' then |
5 | assert clk'stable(HOLD_TIME) report "Hold violation!!" severity error; |
6 | end if; |
7 | end process; |
This is only one of many possible ways to solve the problem
For Shclumpf: Right.. I need this! But in your example the thold and setup are positive values. I need check the violation if the thold is positive and tsetup is negative also. I need check the violation if the tsetup is positive and thold is negative also.
Another option is the keyword 'now'. It represents the current simulation time. You can store the timestamp of any event and calculate with the values.
Luca M. wrote: > I need check Again: in real life on real hardware or just for simulation? And: think about my other questions also. Try to answer them, as I try to help you...
Schlumpf wrote: > Did you understand the principle of the given examples? Yes.. but the setup and old Times can to be negative in complex hardware. Normally are positive in simple flop.
Lothar M. wrote: > Luca M. wrote: >> I need check > Again: in real life on real hardware or just for simulation? > > And: think about my other questions also. Try to answer them, as I try > to help you... Just simulation
If you understood the principle it should be easy for you to adapt the examples to negative values. Or use the keyword now. If you have different cases dependent of positive or negative values you can use the keyword 'if' :) But anyway: What is the sense of that all? Du you want to simulate a backannotated design? As Lothar said: it doesn't make sense..
Schlumpf wrote: > If you understood the principle it should be easy for you to adapt the > examples to negative values. > > Or use the keyword now. > > If you have different cases dependent of positive or negative values you > can use the keyword 'if' :) > > But anyway: > What is the sense of that all? > Du you want to simulate a backannotated design? > As Lothar said: it doesn't make sense.. Yes. With a model of complex flop i can simulate my fpga design to ensure set_output_delay is right.
If the design is synchronous or if the clocks of different domains are in a fixed and known phase relation you can use constraints. If there are asynchronous paths you can report and check the delay of these paths after PaR. There is no need to simulate. And even if you simulate you have to make a simulation for all possible phases between the clocks. And the number of these is infinite..
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