EmbDev.net

Forum: FPGA, VHDL & Verilog cobverting 64 bit to 32 bit.


Author: slim_pga (Guest)
Posted on:

Rate this post
0 useful
not useful
i have alu that has a 32 bit input, the multiplier outputs 64 bits, but 
i need the result of the multiplction to be in 32 bit so i could load it 
into a 32 bit register.

dose anyone has any idea how can convert the 64 bit output to 32bit?

Author: Lothar M. (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
slim_pga wrote:
> dose anyone has any idea how can convert the 64 bit output to 32bit?
The usual ways are to truncate the first or the last 32 bits of the 
result.

What ist the highest number that will show up in the 64bit result?
Will it fit in a 32 bit number?

E.g. when the highest number to be calculated is 100000 x 100000 then 
simply truncate the first 32 bits, because they will hold no necessary 
information...

Author: slim_pga (Guest)
Posted on:

Rate this post
0 useful
not useful
i have a 32bit signale called multi_out. and a mux that inputs 32bit as 
well.
the thing is, that the multi_out is connected between my multiplier 
output ans mux input.
the mux and evrything else in the system works on 32 bit.

here is the last part of the code:
signal add_sub_out : std_logic_vector (31 downto 0); 
signal multi_out : std_logic_vector (63 downto 0); 
begin 
alu_add_sub : adder_subtractor port map (leftin,rightin,opcode(0),negative,add_sub_out); 
alu_multi : Multiplier_VHDL port map (leftin,rightin,multi_out); 
mux : alu_mux port map (add_sub_out,multi_out (31 downto 0),opcode(1),res); 
end struc; 
in the one to last line i tried to connect the multi_out signal to the 
first 32 bists of the multiplier output. (my profesor said its cool to 
do that for our project) but it dosent work.

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
slim_pga wrote:
> but it dosent work.
How did you find that out?


> in the one to last line i tried to connect the multi_out signal to the
> first 32 bists of the multiplier output.
The "first" bits (starting from left like reading a text) are "63 downto 
32".
What you do is to use the 32 lower bits and that is what I suggested.

In reality this assignmet by location is not a good idea:
mux : alu_mux port map (add_sub_out,multi_out (31 downto 0),opcode(1),res);
Its just laziness during writing...

: Edited by Moderator
Author: M. (Guest)
Posted on:

Rate this post
0 useful
not useful
Lothar M. wrote:
> In reality this assignmet by location is not a good idea:mux : alu_mux
> port map (add_sub_out,multi_out (31 downto 0),opcode(1),res);
> Its just laziness during writing...

How would you write it then?

Author: Lothar M. (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
I would use explicit declared assignments like that
http://www.lothar-miller.de/s9y/archives/57-Sinusausgabe-mit-PWM.html

But that's (hopefully) not the problem here...

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig