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Forum: FPGA, VHDL & Verilog force input in simulation wrong.


von fuck_modelsim (Guest)


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this software is a nightmare!!

i have a simualtion running, it is a 32bit multiplier.
but for some reason when i force a "10" it outputs "16".
so for example if i try to multiplie 10*2 it gives me the result 16*2 = 
32;
i put the radix in decimal but it still goes on like this. why?

btw, its like that with all the numbers with zero, meaning 20 is 32.

von Lothar M. (lkmiller) (Moderator)


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fuck_modelsim wrote:
> when i force
That "forcing" thing is the wrong way to s(t)imulate a HDL design. Use a 
test bench insted.

> but for some reason when i force a "10" it outputs "16".
Obviously the 10 is a hexadecimal number. Thats fairly usual in 
hardware design...

: Edited by Moderator
von ee_vhdl (Guest)


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Lothar M. wrote:
> fuck_modelsim wrote:
>> when i force
> That "forcing" thing is the wrong way to s(t)imulate a HDL design. Use a
> test bench insted.
>
>> but for some reason when i force a "10" it outputs "16".
> Obviously the 10 is a hexadecimal number. Thats fairly usual in
> hardware design...

can u explain to me what is a test bench and how do i do one?
i know its super basic.. the thing is my college provided just 3 classes 
on vhdl and now they want us to create an intire project with it.

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