Hi all. I have question. my code is module pulsing(OUT, an1, an2, or1); input wire an1, an2, or1; output wire OUT; wire afa; and andik(afa,an1,an2); or orik(OUT,afa,or1); endmodule I got after synthesis one 3bit LUT result, but I really need 2 different LUTS . How can I implement it without any sequential logic(just wires and LUTs)? Thanks!
During the synthesis the two separate two-bit operations and and or are optimized into a single three but operation in the form of a LUT. Usually you would only need these as separate operations for debugging or if the intermediate signal is needed in the design, too. Since it is not used again and not defined as an output, I'm assuming you just want to debug. In that case, you can use directives for the synthesizer to keep that signal or simulate your design without running the synthesis.
Bogdan wrote: > after synthesis one 3bit LUT When you do nothing then this will always result in a single LUT, because with a 4-input LUT you can do every logic with up to 4 inputs. Yo have only 3 inputs and 1 output. That fits perfectly in a 4-input LUT. And the final aim of the toolchain is to get the fastest logic with the smallest footprint out of your description. > but I really need 2 different LUTS Why that? Then the result will be slower and will need more ressources on your silicon. > How can I implement it without any sequential logic(just wires and LUTs)? Use (as already said) the "keep" attribute for the afa wire. But I can see absolutely no need for that, because it is not needed for the function of this logic: when you look at the 4 FPGA pins in the real world you will see no difference in reaction between those two implementations.
: Edited by Moderator