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Forum: FPGA, VHDL & Verilog Problem with ultrasonic sensor,


Author: Luis Alfredo (Guest)
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Hello, I am trying to make a FSM to measure distance with an Ultrasonic 
sensor, but I cant seem to get rid of this latches and make my design 
work, i would very much appreciate any help or comment you could give me 
about how to fix it, thanks
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity Ultrasonic_Final is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Echo : in  STD_LOGIC;
           Trig : out  STD_LOGIC;
           LEDs : out  STD_LOGIC_VECTOR (7 downto 0));
end Ultrasonic_Final;

architecture Ultrasonic_Final_Arch of Ultrasonic_Final is
  -- Any name can be used for the states
  -- The state coding given below is binary, which is the default
  -- Other state codings could have been used.
  type state_values is (st_wait,st_trigger,st_hold,st_echo);
  signal next_state, present_state : state_values;
  
  -- Signals used by the Frequency divider
  constant Fosc      : integer := 100_000_000;      -- Oscillator Frequency for Nexys3 board
  constant Fdiv      : integer := 1_000_000;              -- Desired Timebase Frequency
  constant CtaMax    : integer := Fosc / Fdiv;    -- Maximum count to obtain desired outputfreq
  signal   Cont      : integer range 0 to CtaMax; -- Define the counter
  signal   Timebase  : std_logic;             -- Flag used to indicate that timebase has ellapsed
  
  -- Cosants and signals for Ultrasonic sensor
  constant twait    : integer                    := 500_000;
  constant ttrig    : integer                    := 3;
  signal   tcount   : integer range 0 to 18_500  := 0;
  signal   tstate   : integer range 0 to 1000000 := 0;
  signal   duracion : integer                    := 0;
  signal   tiempo   : integer range 0 to 18_500  := 0;
  signal   centim   : STD_LOGIC_VECTOR(7 downto 0);
  signal   seg      : integer;

begin
  -- Frequency divider process to obtain a Timebase signal used by the FSM
  FreqDiv: process(Rst,Clk)
  begin
    if Rst = '1' then
     Cont <= 0;
   elsif (rising_edge(Clk)) then
     if Cont = CtaMax-1 then
        Cont     <= 0;
        Timebase <= '1';
      else      
       Cont     <= Cont + 1;
       Timebase <= '0';
     end if;
   end if;
  end process FreqDiv;
  
  -- State Register Process
  -- Holds the current state of the FSM
  statereg: process (Clk,Rst)
  begin
    -- Asynchronous Reset
    if Rst = '1' then
     present_state <= st_wait;
   elsif rising_edge(Clk) then
     if Timebase = '1' then
        if duracion = tstate then
         present_state <= next_state;
        duracion      <= 0;
       else 
         duracion <= duracion + 1;
       end if;
    end if;
   end if;
  end process statereg;
  
  -- Define the Next-State Logic Process
  -- Will obtain the next state based on the inputs and current state
  fsm: process (present_state, Echo, tcount)
  begin
    case present_state is
      when st_wait    => 
      if (Echo = '0') then 
        next_state <= st_trigger; 
        tstate     <= ttrig;
      else 
        next_state <= st_echo; 
        tstate     <= 1;
      end if;
      when st_trigger =>
      if (Echo = '0') then
        next_state <= st_hold;
        tstate     <= 1;
      else 
        next_state <= st_echo; 
        tstate     <= 1;  
      end if;
      when st_hold    =>
      if (Echo = '0') then
        next_state <= st_hold;
        tstate     <= 1;
      elsif (Echo = '1') then
        next_state <= st_echo;
        tstate     <= 1;
      end if;
      when st_echo    =>
      if (Echo = '0') then
        next_state <= st_wait;
        tstate     <= twait;
        tcount     <= 0;
      elsif (Echo = '1') then
        next_state <= st_echo;
        tstate     <= 1;
        tcount     <= tcount + 1;
      end if;
      when others =>
        next_state <= st_wait;
        tstate     <= twait;
        tcount     <= 0;
   end case;
  end process fsm;
    
  tiempo <= tcount;
  seg    <= (tiempo/(1*10**6));
  centim <= CONV_STD_LOGIC_VECTOR((34320*seg), 8);
  
  -- If implementing a Moore Machine use the following process
  -- The output of a Moore Machine is determined by the present_state only
  output: process (present_state, centim)
  begin
    case present_state is
     when st_wait    =>
      Trig <= '0';
      LEDs <= centim;
     when st_trigger =>
      Trig <= '1';
      LEDs <= centim;
     when st_hold    =>
      Trig <= '0';
      LEDs <= centim;
     when st_echo    =>
      Trig <= '0';
      LEDs <= centim;
      when others  =>
      Trig <= '0';
      LEDs <= "11111111";
     end case;
  end process output;

end Ultrasonic_Final_Arch;

   --WARNINGS--

WARNING:Xst:737 - Found 1-bit latch for signal <tcount<14>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<13>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<12>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<11>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<10>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<9>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<8>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<7>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<6>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<5>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<4>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<3>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<2>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<1>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<0>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:2677 - Node <tcount_12> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_13> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_9> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_11> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_10> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_8> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_7> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_4> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_6> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_5> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_3> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_2> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_1> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_0> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_14> of sequential type is unconnected in 
block <Ultrasonic_Final>.

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
Posted on:

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Luis Alfredo wrote:
> but I cant seem to get rid of this latches
This is the problem:
        tcount     <= tcount + 1;
That is a combinatorial loop, its a counter without registers. Thats the 
most common problem when using the two-process style. You must change it 
somehow like this:
:
  -- State Register Process
  -- Holds the current state of the FSM
  statereg: process (Clk,Rst)
  begin
    -- Asynchronous Reset
   if Rst = '1' then
     :
   elsif rising_edge(Clk) then
     tcount <= tcount_next;
     :
     :
   end if;
  end process statereg;
:
:
        tcount_next  <= tcount + 1;
:

A hint:
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
Never ever use both of those math packages together. You will get 
strange error messages and curious behaviour now and then due to 
multiple type definitions. The numeric_std has all you will need.


BTW: pls use the [ vhdl ] tags to wrap your code (as described above 
each edit box)
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: Edited by Moderator

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