Problem with ultrasonic sensor,

Luis Alfredo Guest #5636989
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Hello, I am trying to make a FSM to measure distance with an Ultrasonic 
sensor, but I cant seem to get rid of this latches and make my design 
work, i would very much appreciate any help or comment you could give me 
about how to fix it, thanks

1
library IEEE;

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use IEEE.std_logic_1164.all;

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use IEEE.numeric_std.all;

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use IEEE.std_logic_unsigned.all;

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use IEEE.std_logic_arith.all;

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entity Ultrasonic_Final is

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    Port ( Clk : in  STD_LOGIC;

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           Rst : in  STD_LOGIC;

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           Echo : in  STD_LOGIC;

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           Trig : out  STD_LOGIC;

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           LEDs : out  STD_LOGIC_VECTOR (7 downto 0));

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end Ultrasonic_Final;

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architecture Ultrasonic_Final_Arch of Ultrasonic_Final is

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  -- Any name can be used for the states

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  -- The state coding given below is binary, which is the default

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  -- Other state codings could have been used.

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  type state_values is (st_wait,st_trigger,st_hold,st_echo);

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  signal next_state, present_state : state_values;

21
  

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  -- Signals used by the Frequency divider

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  constant Fosc      : integer := 100_000_000;      -- Oscillator Frequency for Nexys3 board

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  constant Fdiv      : integer := 1_000_000;              -- Desired Timebase Frequency

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  constant CtaMax    : integer := Fosc / Fdiv;    -- Maximum count to obtain desired outputfreq

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  signal   Cont      : integer range 0 to CtaMax; -- Define the counter

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  signal   Timebase  : std_logic;             -- Flag used to indicate that timebase has ellapsed

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  -- Cosants and signals for Ultrasonic sensor

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  constant twait    : integer                    := 500_000;

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  constant ttrig    : integer                    := 3;

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  signal   tcount   : integer range 0 to 18_500  := 0;

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  signal   tstate   : integer range 0 to 1000000 := 0;

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  signal   duracion : integer                    := 0;

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  signal   tiempo   : integer range 0 to 18_500  := 0;

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  signal   centim   : STD_LOGIC_VECTOR(7 downto 0);

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  signal   seg      : integer;

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begin

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  -- Frequency divider process to obtain a Timebase signal used by the FSM

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  FreqDiv: process(Rst,Clk)

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  begin

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    if Rst = '1' then

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     Cont <= 0;

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   elsif (rising_edge(Clk)) then

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     if Cont = CtaMax-1 then

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        Cont     <= 0;

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        Timebase <= '1';

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      else      

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       Cont     <= Cont + 1;

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       Timebase <= '0';

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     end if;

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   end if;

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  end process FreqDiv;

55
  

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  -- State Register Process

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  -- Holds the current state of the FSM

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  statereg: process (Clk,Rst)

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  begin

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    -- Asynchronous Reset

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    if Rst = '1' then

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     present_state <= st_wait;

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   elsif rising_edge(Clk) then

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     if Timebase = '1' then

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        if duracion = tstate then

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         present_state <= next_state;

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        duracion      <= 0;

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       else 

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         duracion <= duracion + 1;

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       end if;

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    end if;

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   end if;

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  end process statereg;

74
  

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  -- Define the Next-State Logic Process

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  -- Will obtain the next state based on the inputs and current state

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  fsm: process (present_state, Echo, tcount)

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  begin

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    case present_state is

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      when st_wait    => 

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      if (Echo = '0') then 

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        next_state <= st_trigger; 

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        tstate     <= ttrig;

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      else 

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        next_state <= st_echo; 

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        tstate     <= 1;

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      end if;

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      when st_trigger =>

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      if (Echo = '0') then

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        next_state <= st_hold;

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        tstate     <= 1;

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      else 

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        next_state <= st_echo; 

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        tstate     <= 1;  

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      end if;

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      when st_hold    =>

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      if (Echo = '0') then

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        next_state <= st_hold;

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        tstate     <= 1;

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      elsif (Echo = '1') then

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        next_state <= st_echo;

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        tstate     <= 1;

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      end if;

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      when st_echo    =>

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      if (Echo = '0') then

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        next_state <= st_wait;

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        tstate     <= twait;

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        tcount     <= 0;

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      elsif (Echo = '1') then

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        next_state <= st_echo;

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        tstate     <= 1;

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        tcount     <= tcount + 1;

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      end if;

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      when others =>

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        next_state <= st_wait;

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        tstate     <= twait;

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        tcount     <= 0;

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   end case;

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  end process fsm;

120
    

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  tiempo <= tcount;

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  seg    <= (tiempo/(1*10**6));

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  centim <= CONV_STD_LOGIC_VECTOR((34320*seg), 8);

124
  

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  -- If implementing a Moore Machine use the following process

126
  -- The output of a Moore Machine is determined by the present_state only

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  output: process (present_state, centim)

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  begin

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    case present_state is

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     when st_wait    =>

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      Trig <= '0';

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      LEDs <= centim;

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     when st_trigger =>

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      Trig <= '1';

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      LEDs <= centim;

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     when st_hold    =>

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      Trig <= '0';

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      LEDs <= centim;

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     when st_echo    =>

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      Trig <= '0';

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      LEDs <= centim;

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      when others  =>

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      Trig <= '0';

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      LEDs <= "11111111";

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     end case;

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  end process output;

147


148
end Ultrasonic_Final_Arch;


   --WARNINGS--

WARNING:Xst:737 - Found 1-bit latch for signal <tcount<14>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<13>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<12>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<11>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<10>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<9>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<8>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<7>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<6>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<5>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<4>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<3>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<2>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<1>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:737 - Found 1-bit latch for signal <tcount<0>>. Latches may 
be generated from incomplete case or if statements. We do not recommend 
the use of latches in FPGA/CPLD designs, as they may lead to timing 
problems.
WARNING:Xst:2677 - Node <tcount_12> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_13> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_9> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_11> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_10> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_8> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_7> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_4> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_6> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_5> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_3> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_2> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_1> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_0> of sequential type is unconnected in 
block <Ultrasonic_Final>.
WARNING:Xst:2677 - Node <tcount_14> of sequential type is unconnected in 
block <Ultrasonic_Final>.
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Lothar M. Moderator (Company: Titel) #5637046
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Luis Alfredo wrote:
> but I cant seem to get rid of this latches
This is the problem:
1
        tcount     <= tcount + 1;

That is a combinatorial loop, its a counter without registers. Thats the 
most common problem when using the two-process style. You must change it 
somehow like this:
1
:

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  -- State Register Process

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  -- Holds the current state of the FSM

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  statereg: process (Clk,Rst)

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  begin

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    -- Asynchronous Reset

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   if Rst = '1' then

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     :

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   elsif rising_edge(Clk) then

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     tcount <= tcount_next;

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     :

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     :

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   end if;

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  end process statereg;

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:

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:

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        tcount_next  <= tcount + 1;

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:


A hint:
1
use IEEE.numeric_std.all;

2
use IEEE.std_logic_unsigned.all;

3
use IEEE.std_logic_arith.all;

Never ever use both of those math packages together. You will get 
strange error messages and curious behaviour now and then due to 
multiple type definitions. The numeric_std has all you will need.


BTW: pls use the [ vhdl ] tags to wrap your code (as described above 
each edit box)
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