UART transmitter

Hareesh M. OP (Company: Mindteck) #5629289
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Hi all,
I have written code for UART transmitter with 9600 baud rate. The thing 
is when i simulate the code using modelsim the UART signals are find but 
when i try to use terminal for transmission there is no output.

1
Library ieee;

2
use ieee.std_logic_1164.all;

3
use ieee.numeric_std.all;

4


5
entity uart_tx is

6


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  generic (

8
          baud_rate_divisor : integer:=520

9
        );

10
  

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  port (

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        i_inclk         : in std_logic; --Clock input 50Mhz

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        i_reset          : in std_logic; --Reset for UART transmission

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        i_tx_data_bits    : in std_logic_vector(0 to 7); --8 bits of data to be send

15
        i_tx_start      : in std_logic; --

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        o_tx_done      : out std_logic; --Bit to indicate transmission done

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        o_tx_line_busy    : out std_logic; --Bit to indicate busy

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        led_testing      : out std_logic;

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        test_led        : out std_logic;

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        o_serial_data    : out std_logic --Data to be send serially

21
        

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      );

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end uart_tx;

25


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architecture behav of uart_tx is

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  type transmitter_state is(tx_idle,tx_start,tx_data,tx_stop);

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  signal tx_state:transmitter_state:=tx_idle;

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  signal baud_rate_clk    : std_logic:='0';

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  signal clk_divider     : integer range 0 to 530:= 0;

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  signal tx_data_byte    : std_logic_vector(0 to 7);

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  signal tx_done_bit    : std_logic;

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  signal out_clk         : std_logic:='0';

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  signal index_counter    : integer range 0 to 7;

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begin

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  process(i_reset,i_inclk)

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  begin

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    if(i_reset='0')then

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      clk_divider<=0;

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    elsif(rising_edge(i_inclk))then

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      if(clk_divider<baud_rate_divisor)then

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        clk_divider <= clk_divider+1;        

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      else

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        clk_divider <= 0;

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        baud_rate_clk <= not(baud_rate_clk);

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      end if;

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    end if;

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  end process;

55
  

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  led_testing <= baud_rate_clk;

57


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  process(baud_rate_clk)

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  begin

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    if(rising_edge(baud_rate_clk))then

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      case tx_state is

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        when tx_idle =>

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          o_tx_done      <= '0';

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          o_tx_line_busy <= '0';

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          index_counter  <=  0;

67
          

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          if(i_tx_start='0')then

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            tx_data_byte <= i_tx_data_bits;

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            tx_state <= tx_start;

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          else

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            tx_state <= tx_idle;

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          end if;

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        when tx_start =>

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          o_tx_line_busy <= '1';

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          o_serial_data <= '0';

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          tx_state <= tx_data;

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        when tx_data =>

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          o_serial_data <= tx_data_byte(index_counter);

82
          

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          if(index_counter<7)then            

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            index_counter <= index_counter+1;

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            tx_state <= tx_data;

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          else

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            tx_state <= tx_stop;

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          end if;

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        when tx_stop =>

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          o_serial_data <= '1';

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          o_tx_done <= '1';

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          tx_state <= tx_idle;

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        when others =>

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          tx_state <= tx_idle;

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      end case;

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    end if;

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  end process;

100
  

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  test_led <= i_tx_start;

102


103
end behav;



and the test bench for above code is give

1
LIBRARY ieee  ; 

2
LIBRARY std  ; 

3
USE ieee.NUMERIC_STD.all  ; 

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USE ieee.std_logic_1164.all  ; 

5
USE ieee.std_logic_textio.all  ; 

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USE ieee.std_logic_unsigned.all  ; 

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USE std.textio.all  ; 

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ENTITY tx_test_bench  IS 

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  GENERIC (

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    baud_rate_divisor  : INTEGER   := 520 ); 

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END ; 

12
 

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ARCHITECTURE tx_test_bench_arch OF tx_test_bench IS

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  SIGNAL i_inclk   :  STD_LOGIC  ; 

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  SIGNAL led_testing : STD_LOGIC;

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  SIGNAL i_tx_start   :  STD_LOGIC  ; 

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  SIGNAL o_tx_line_busy   :  STD_LOGIC  ;

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  SIGNAL i_tx_data_bits   :  STD_LOGIC_VECTOR (0 to 7)  ; 

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  SIGNAL o_serial_data   :  STD_LOGIC  ; 

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  SIGNAL o_tx_done   :  STD_LOGIC  ; 

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  SIGNAL i_reset   :  STD_LOGIC  ; 

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  COMPONENT uart_tx  

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    GENERIC ( 

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      baud_rate_divisor  : INTEGER  );  

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    PORT ( 

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      i_inclk  : in STD_LOGIC ;

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    led_testing : out STD_LOGIC;  

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      i_tx_start  : in STD_LOGIC ; 

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      o_tx_line_busy  : out STD_LOGIC ; 

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      i_tx_data_bits  : in STD_LOGIC_VECTOR (0 to 7); 

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      o_serial_data  : out STD_LOGIC ; 

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      o_tx_done  : out STD_LOGIC ; 

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      i_reset  : in STD_LOGIC ); 

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  END COMPONENT ; 

36
BEGIN

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  DUT  : uart_tx  

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    GENERIC MAP ( 

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      baud_rate_divisor  => baud_rate_divisor   )

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    PORT MAP ( 

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      i_tx_start   => i_tx_start  ,

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      i_inclk   => i_inclk  ,

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      i_tx_data_bits   => i_tx_data_bits  ,

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      o_serial_data   => o_serial_data  ,

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      o_tx_line_busy   => o_tx_line_busy  ,

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      o_tx_done   => o_tx_done  ,

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    led_testing => led_testing,

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      i_reset   => i_reset   ) ; 

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50


51


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-- "Clock Pattern" : dutyCycle = 50

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-- Start Time = 0 ps, End Time = 100 ms, Period = 20 ns

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  Process

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  Begin

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   i_inclk  <= '0'  ;

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  wait for 10 ns ;

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   i_inclk  <= '1'  ;

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  wait for 10 ns ;

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-- dumped values till 100 ps

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 End Process;

63


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-- "Constant Pattern"

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-- Start Time = 0 ps, End Time = 10 ps, Period = 0 ps

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  Process

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  Begin

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  wait until rising_edge(led_testing);

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  i_tx_start  <= '1'  ;

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  i_tx_data_bits  <= "10101010"  ;

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  wait until rising_edge(led_testing);

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  i_tx_start <= '0';

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  wait until o_tx_done<='1';

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---- dumped values till 10 ps

76
  wait;

77
 End Process;

78


79
end;



iam also attaching the simulated output
Attached files:
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Lothar M. Moderator (Company: Titel) #5629315
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Hareesh M. wrote:
> the test bench for above code is
Drive i_reset with a defined value.

> when i try to use terminal for transmission there is no output.
What terminal? Do you mean when you implement that design on real 
hardware? What does a scope or a logic analyzer show?

This is bad design practice:
1
    baud_rate_clk <= not(baud_rate_clk);

2
:

3
:

4
    if(rising_edge(baud_rate_clk))then

Don't use divided locally distributed clocks in a FPGA. Instead use 
clock enables and only one clock overall the FPGA!
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Hareesh M. OP (Company: Mindteck) #5629376
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Lothar M. wrote:
> Hareesh M. wrote:
>> the test bench for above code is
> Drive i_reset with a defined value.

Ok i will do it. Thanks for the comment
>
>> when i try to use terminal for transmission there is no output.
> What terminal? Do you mean when you implement that design on real
> hardware? What does a scope or a logic analyzer show?

I have connected the
1
o_serial_data

 to a gpio in fpga dev board and used a rs232 to usb cable to see the 
output in pc
>
> This is bad design practice:
>
1
>     baud_rate_clk <= not(baud_rate_clk);

2
> :

3
> :

4
>     if(rising_edge(baud_rate_clk))then

5
>

> Don't use divided locally distributed clocks in a FPGA. Instead use
> clock enables and only one clock overall the FPGA!

Thanks for your comment, but if i use a enable signal will i get a clock 
as output. Does 9600bps baud rate generation is fine?
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Lothar M. Moderator (Company: Titel) #5629388
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Hareesh M. wrote:
> I have connected the o_serial_data to a gpio in fpga dev board and used
> a rs232 to usb cable to see the output in pc
What cable?
You know, that RS232 has very different signal levels than your FPGA 
output pin?

> Does 9600bps baud rate generation is fine?
Not the way you do it.

> but if i use a enable signal will i get a clock as output.
???
You got lost somewhere. A clock enable is simply implemented in your 
code:
1
  signal baud_tic   : std_logic:='0'; -- the clock enable signal

2
:

3
:

4
  process(i_reset,i_inclk)

5
  begin

6
    if(i_reset='0')then

7
      clk_divider<=0;

8
    elsif(rising_edge(i_inclk))then   -- ONLY ONE AND THE SAME CLOCK in the whole design!

9
      if(clk_divider<1234)then        -- adapt this value

10
        clk_divider <= clk_divider+1; 

11
        baud_tic <= '0';

12
      else

13
        clk_divider <= 0;

14
        baud_tic <= '1';              -- clock enable active for one clock cycle

15
      end if;

16
    end if;

17
  end process;

18
  

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  led_testing <= baud_rate_clk;

20


21
  process(i_inclk)

22
  begin

23
    if(rising_edge(i_inclk))then      -- ONLY ONE AND THE SAME CLOCK in the whole design!

24
    if baud_tic='1' then              -- this is the clock enable

25
      case tx_state is

26
        when tx_idle =>

27
          o_tx_done      <= '0';

28
          o_tx_line_busy <= '0';

29
          index_counter  <=  0;

30
:

31
:
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Hareesh M. OP (Company: Mindteck) #5629400
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Lothar M. wrote:
> Hareesh M. wrote:
>> I have connected the o_serial_data to a gpio in fpga dev board and used
>> a rs232 to usb cable to see the output in pc
> What cable?
> You know, that RS232 has very different signal levels than your FPGA
> output pin?

The gpio which i have connected in fpga dev board is of 3.3V and the 
rs232 voltage level range between  +3 to +15 volts or the range −3 to 
−15
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Lothar M. Moderator (Company: Titel) #5629410
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Hareesh M. wrote:
> The gpio which i have connected in fpga dev board is of 3.3V and the
> rs232 voltage level range between  +3 to +15 volts or the range −3 to −15
And does this fit togeher? And does the polarity of a '1' and a '0' fit 
together?

A hint: look for a levelshifter like MAX3232

Or better: look for a "ttl 3V RS232-USB adapter"
https://www.google.com/search?q=ttl+3V+RS232-USB+adapter
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Hareesh M. OP (Company: Mindteck) #5629423
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Lothar M. wrote:
> Hareesh M. wrote:
>> The gpio which i have connected in fpga dev board is of 3.3V and the
>> rs232 voltage level range between  +3 to +15 volts or the range −3 to −15
> And does this fit togeher? And does the polarity of a '1' and a '0' fit
> together?
>
> A hint: look for a levelshifter like MAX3232
>
> Or better: look for a "ttl 3V RS232-USB adapter"
> https://www.google.com/search?q=ttl+3V+RS232-USB+adapter

I have attached the cable picture.And i tried to probe the signal in CRO 
also, but nothing is coming.
Attached files:
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Lothar M. Moderator (Company: Titel) #5629694
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Hareesh M. wrote:
> i have connected the signal i_tx_start to a push button.
Just a simple button? Without a additional pullup or a pulldown? And 
what signal level do you measure at that input?

What happens when you change your code in a way that the transmission 
always starts on its own in an endless loop? For debugging I would add 
thre additional LED and set one of them in each state of that FSM to 
see, where the thing stucks.
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Hareesh M. OP (Company: Mindteck) #5629720
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Lothar M. wrote:
> Hareesh M. wrote:
>> i have connected the signal i_tx_start to a push button.
> Just a simple button? Without a additional pullup or a pulldown? And
> what signal level do you measure at that input?

A button with a pull down.

>
> What happens when you change your code in a way that the transmission
> always starts on its own in an endless loop? For debugging I would add
> thre additional LED and set one of them in each state of that FSM to
> see, where the thing stucks.

Actually i have tried this, and the led is set when code go into each 
state.
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Hareesh M. OP (Company: Mindteck) #5629734
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Lothar M. wrote:
> Hareesh M. wrote:
>> I have connected the o_serial_data to a gpio in fpga dev board and used
>> a rs232 to usb cable to see the output in pc
> What cable?
> You know, that RS232 has very different signal levels than your FPGA
> output pin?
>
>> Does 9600bps baud rate generation is fine?
> Not the way you do it.

Could you please suggest the changes??
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Lothar M. Moderator (Company: Titel) #5629784
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Hareesh M. wrote:
> Could you please suggest the changes??
I did. With the "clock enable" the design is whats called "synchonous".

Hareesh M. wrote:
> Actually i have tried this, and the led is set when code go into each
> state.
So you see on the LED your design stepping throughout the 4 states? But 
you don't see any changes on o_serial_data although its set in 
tx_stop and it reset in tx_start?
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hareesh Guest #5629906
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Lothar M. wrote:
> Hareesh M. wrote:
>> Could you please suggest the changes??
> I did. With the "clock enable" the design is whats called "synchonous".
>
> Hareesh M. wrote:
>> Actually i have tried this, and the led is set when code go into each
>> state.
> So you see on the LED your design stepping throughout the 4 states? But
> you don't see any changes on o_serial_data although its set in
> tx_stop and it reset in tx_start?

Hi  Lothar ,
The signals are coming in o_serial_data. the issue was with the i_reset 
signal.
Thanks for your valuable comments. Now i need to use a usb to serial 
cable to see the signals in pc.
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