Hi all, I have written code for UART transmitter with 9600 baud rate. The thing is when i simulate the code using modelsim the UART signals are find but when i try to use terminal for transmission there is no output.
1 | Library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.numeric_std.all; |
4 | |
5 | entity uart_tx is |
6 | |
7 | generic ( |
8 | baud_rate_divisor : integer:=520 |
9 | );
|
10 | |
11 | port ( |
12 | i_inclk : in std_logic; --Clock input 50Mhz |
13 | i_reset : in std_logic; --Reset for UART transmission |
14 | i_tx_data_bits : in std_logic_vector(0 to 7); --8 bits of data to be send |
15 | i_tx_start : in std_logic; -- |
16 | o_tx_done : out std_logic; --Bit to indicate transmission done |
17 | o_tx_line_busy : out std_logic; --Bit to indicate busy |
18 | led_testing : out std_logic; |
19 | test_led : out std_logic; |
20 | o_serial_data : out std_logic --Data to be send serially |
21 | |
22 | );
|
23 | |
24 | end uart_tx; |
25 | |
26 | architecture behav of uart_tx is |
27 | |
28 | type transmitter_state is(tx_idle,tx_start,tx_data,tx_stop); |
29 | signal tx_state:transmitter_state:=tx_idle; |
30 | |
31 | signal baud_rate_clk : std_logic:='0'; |
32 | signal clk_divider : integer range 0 to 530:= 0; |
33 | signal tx_data_byte : std_logic_vector(0 to 7); |
34 | signal tx_done_bit : std_logic; |
35 | signal out_clk : std_logic:='0'; |
36 | signal index_counter : integer range 0 to 7; |
37 | |
38 | |
39 | |
40 | |
41 | begin
|
42 | process(i_reset,i_inclk) |
43 | begin
|
44 | if(i_reset='0')then |
45 | clk_divider<=0; |
46 | elsif(rising_edge(i_inclk))then |
47 | if(clk_divider<baud_rate_divisor)then |
48 | clk_divider <= clk_divider+1; |
49 | else
|
50 | clk_divider <= 0; |
51 | baud_rate_clk <= not(baud_rate_clk); |
52 | end if; |
53 | end if; |
54 | end process; |
55 | |
56 | led_testing <= baud_rate_clk; |
57 | |
58 | process(baud_rate_clk) |
59 | begin
|
60 | if(rising_edge(baud_rate_clk))then |
61 | |
62 | case tx_state is |
63 | when tx_idle => |
64 | o_tx_done <= '0'; |
65 | o_tx_line_busy <= '0'; |
66 | index_counter <= 0; |
67 | |
68 | if(i_tx_start='0')then |
69 | tx_data_byte <= i_tx_data_bits; |
70 | tx_state <= tx_start; |
71 | else
|
72 | tx_state <= tx_idle; |
73 | end if; |
74 | |
75 | when tx_start => |
76 | o_tx_line_busy <= '1'; |
77 | o_serial_data <= '0'; |
78 | tx_state <= tx_data; |
79 | |
80 | when tx_data => |
81 | o_serial_data <= tx_data_byte(index_counter); |
82 | |
83 | if(index_counter<7)then |
84 | index_counter <= index_counter+1; |
85 | tx_state <= tx_data; |
86 | else
|
87 | tx_state <= tx_stop; |
88 | end if; |
89 | |
90 | when tx_stop => |
91 | o_serial_data <= '1'; |
92 | o_tx_done <= '1'; |
93 | tx_state <= tx_idle; |
94 | |
95 | when others => |
96 | tx_state <= tx_idle; |
97 | end case; |
98 | end if; |
99 | end process; |
100 | |
101 | test_led <= i_tx_start; |
102 | |
103 | end behav; |
and the test bench for above code is give
1 | LIBRARY ieee ; |
2 | LIBRARY std ; |
3 | USE ieee.NUMERIC_STD.all ; |
4 | USE ieee.std_logic_1164.all ; |
5 | USE ieee.std_logic_textio.all ; |
6 | USE ieee.std_logic_unsigned.all ; |
7 | USE std.textio.all ; |
8 | ENTITY tx_test_bench IS |
9 | GENERIC ( |
10 | baud_rate_divisor : INTEGER := 520 ); |
11 | END ; |
12 | |
13 | ARCHITECTURE tx_test_bench_arch OF tx_test_bench IS |
14 | SIGNAL i_inclk : STD_LOGIC ; |
15 | SIGNAL led_testing : STD_LOGIC; |
16 | SIGNAL i_tx_start : STD_LOGIC ; |
17 | SIGNAL o_tx_line_busy : STD_LOGIC ; |
18 | SIGNAL i_tx_data_bits : STD_LOGIC_VECTOR (0 to 7) ; |
19 | SIGNAL o_serial_data : STD_LOGIC ; |
20 | SIGNAL o_tx_done : STD_LOGIC ; |
21 | SIGNAL i_reset : STD_LOGIC ; |
22 | |
23 | COMPONENT uart_tx |
24 | GENERIC ( |
25 | baud_rate_divisor : INTEGER ); |
26 | PORT ( |
27 | i_inclk : in STD_LOGIC ; |
28 | led_testing : out STD_LOGIC; |
29 | i_tx_start : in STD_LOGIC ; |
30 | o_tx_line_busy : out STD_LOGIC ; |
31 | i_tx_data_bits : in STD_LOGIC_VECTOR (0 to 7); |
32 | o_serial_data : out STD_LOGIC ; |
33 | o_tx_done : out STD_LOGIC ; |
34 | i_reset : in STD_LOGIC ); |
35 | END COMPONENT ; |
36 | BEGIN
|
37 | DUT : uart_tx |
38 | GENERIC MAP ( |
39 | baud_rate_divisor => baud_rate_divisor ) |
40 | PORT MAP ( |
41 | i_tx_start => i_tx_start , |
42 | i_inclk => i_inclk , |
43 | i_tx_data_bits => i_tx_data_bits , |
44 | o_serial_data => o_serial_data , |
45 | o_tx_line_busy => o_tx_line_busy , |
46 | o_tx_done => o_tx_done , |
47 | led_testing => led_testing, |
48 | i_reset => i_reset ) ; |
49 | |
50 | |
51 | |
52 | -- "Clock Pattern" : dutyCycle = 50
|
53 | -- Start Time = 0 ps, End Time = 100 ms, Period = 20 ns
|
54 | Process
|
55 | Begin
|
56 | i_inclk <= '0' ; |
57 | wait for 10 ns ; |
58 | i_inclk <= '1' ; |
59 | wait for 10 ns ; |
60 | -- dumped values till 100 ps
|
61 | |
62 | End Process; |
63 | |
64 | |
65 | -- "Constant Pattern"
|
66 | -- Start Time = 0 ps, End Time = 10 ps, Period = 0 ps
|
67 | Process
|
68 | Begin
|
69 | wait until rising_edge(led_testing); |
70 | i_tx_start <= '1' ; |
71 | i_tx_data_bits <= "10101010" ; |
72 | wait until rising_edge(led_testing); |
73 | i_tx_start <= '0'; |
74 | wait until o_tx_done<='1'; |
75 | ---- dumped values till 10 ps
|
76 | wait; |
77 | End Process; |
78 | |
79 | end; |
iam also attaching the simulated output
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