Giorgia wrote:
> This code doesn't work because the second, the third and the fourth
> display are late compared to the first one of one clock cycle. Could you
> help me please?
Congratulations, you found what's called "latency". The most easy
solution for that "problem" is, to supply them one clock cycle earlier.
But in the real world with a 50MHz clock its not problem to have one
clock cycle latency here, because then the display is delayed by 20ns.
Your eye will not recognize that...
A few hints beyond that:
1 | z1 : inout STD_LOGIC_VECTOR (6 downto 0);
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Are those really inout ports? If not: why do you declare it that way?
Just for laziness? That's no good idea, believe me.
1 | for k in 6 downto 0 loop
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2 | o1(k)<=z1(k);
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3 | o2(k)<=o1(k);
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4 | o3(k)<=o2(k);
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5 | end loop;
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You can skip the loop and cut this down to
1 | o1 <= z1;
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2 | o2 <= o1;
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3 | o3 <= o2;
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Giorgia wrote:
> I have to write a code to scroll a text (such as "dE1") on a 7-seg
> display using four 7-bit registers connected in a queue-like fashion
Why do you do that so complicated with additional FSM and so on?
Why not the easy way?
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | entity Scroll is
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5 | Port ( clk : in STD_LOGIC;
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6 | rst : in STD_LOGIC;
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7 | z1 : out STD_LOGIC_VECTOR (6 downto 0);
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8 | z2 : out STD_LOGIC_VECTOR (6 downto 0);
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9 | z3 : out STD_LOGIC_VECTOR (6 downto 0);
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10 | z4 : out STD_LOGIC_VECTOR (6 downto 0));
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11 | end Scroll;
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12 |
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13 | architecture Behavioral of Scroll is
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14 |
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15 | signal o1: std_logic_vector(6 downto 0) :="0111101"; -- d
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16 | signal o2: std_logic_vector(6 downto 0) :="1001111"; -- E
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17 | signal o3: std_logic_vector(6 downto 0) :="0110000"; -- 1
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18 | signal o4: std_logic_vector(6 downto 0) :="0000000"; -- blank
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19 |
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20 | begin
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21 |
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22 | pipeline: process(clk,rst)
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23 | begin
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24 | if rst='0' then
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25 | o1<="0111101";
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26 | o2<="1001111";
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27 | o3<="0110000";
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28 | o4<="0000000";
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29 | elsif(clk'event and clk='1') then
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30 | o1 <= o2; -- scroll the text (fairly fast at some MHz clock...)
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31 | o2 <= o3;
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32 | o3 <= o4;
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33 | o4 <= o1;
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34 | end if;
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35 | end process;
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36 |
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37 | z1 <= o1;
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38 | z2 <= o2;
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39 | z3 <= o3;
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40 | z4 <= o4;
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41 |
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42 | end Behavioral;
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BTW: pls wrap your VHDL code with the [vhdl] tokens as described a few
lines over each edit-box.
BTW2: with proper indention your code gets more readable.