Hi, I need to design & verify parametric design, such that my design & verif env will be instantiated twice, each time with different parameters. I usually work with packages for my design, so all of parameters, structs etc are defined there. My questions: Is there a way to write such package so same package will hold same parameter with two different values? (different value for each instance) Thanks!

Ido wrote: > I need to design In what language? > Is there a way to write such package so same package will hold same > parameter with two different values? (different value for each instance) In VHDL there are "generics": one "universal" (=generic) description and two (or more) instances with different (but static) parameters.

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Edited by Moderator

Lothar M. wrote: > Ido wrote: >> I need to design > In what language? > Verilog/system verilog >> Is there a way to write such package so same package will hold same >> parameter with two different values? (different value for each instance) > In VHDL there are "generics": one "universal" (=generic) description and > two (or more) instances with different (but static) parameters. Is there similiar solution in verilog/system verilog? Thanks