EmbDev.net

Forum: FPGA, VHDL & Verilog Procedure in VHDL testbench


Author: Bah (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello there,

I am trying to implement a procedure in my testbench to shorten the 
lenght.
entity tb is
end entity;

architecture sim of tb is

  procedure P_DATA(
      constant ctrl  : in std_logic_vector (8 downto 0);
      constant ht    : in std_logic_vector (16 downto 0);
      constant prd   : in std_logic_vector (16 downto 0))
      is
      variable i_sctrl  :  std_logic_vector (8 downto 0);
      variable i_sprd    :  std_logic_vector (16 downto 0);
      variable i_sht     :  std_logic_vector (16 downto 0);
 begin
     i_sctrl  := ctrl;
     i_sprd   := prd;
     i_sht    := ht;
 end procedure;

  signal i_clk   : std_logic;
  signal i_rst   : std_logic; 
  signal i_sctrl : std_logic_vector (8 downto 0);
  signal i_sprd  : std_logic_vector (16 downto 0;
  Signal i_sht   : std_logic_vector (16 downto 0;
  ....

begin

  -- Data generation
  pr_int : process
  begin
      
      i_rst <= '1';
      i_sctrl <= (others => '0');
      i_sprd  <= (others => '0');
      i_sht   <= (others => '0');
      wait for 5 ns;
      i_rst <= '0';
      wait for 2 ns;
      wait for rising_edge(i_clk);
      P_DATA(X"04", X"0009",X"000A");
      wait for 1 ns;
      wait;

     end process;

end architecture;

When I simulate to above Code my inputs data are all "zero" all the 
time. How can I modify the procedure to get the set values in the 
simulation waveform

Many thanks

Author: Duke Scarring (Guest)
Posted on:

Rate this post
0 useful
not useful
The signals i_sctrl, i_sprd and i_sht are in a diffrent scope, than the 
variables with the same name inside the procedure.

If you want zu use them, you have to add them to the parameter list:
  procedure P_DATA(
      constant ctrl  : in std_logic_vector (8 downto 0);
      constant ht    : in std_logic_vector (16 downto 0);
      constant prd   : in std_logic_vector (16 downto 0);
      signal x_sctrl : out std_logic_vector (8 downto 0);
      signal x_sprd  : out std_logic_vector (16 downto 0);
      signal x_sht   : out std_logic_vector (16 downto 0);
)
      is
 begin
     x_sctrl  <= ctrl;
     x_sprd   <= prd;
     x_sht    <= ht;
 end procedure;

...

P_DATA(X"04", X"0009",X"000A",i_sctrl,i_sprd,i_sht);

Duke

Author: Bah (Guest)
Posted on:

Rate this post
0 useful
not useful
Duke Scarring wrote:
> The signals i_sctrl, i_sprd and i_sht are in a diffrent scope,
> than the
> variables with the same name inside the procedure.
>
> If you want zu use them, you have to add them to the parameter list:
> procedure P_DATA(
>       constant ctrl  : in std_logic_vector (8 downto 0);
>       constant ht    : in std_logic_vector (16 downto 0);
>       constant prd   : in std_logic_vector (16 downto 0);
>       signal x_sctrl : out std_logic_vector (8 downto 0);
>       signal x_sprd  : out std_logic_vector (16 downto 0);
>       signal x_sht   : out std_logic_vector (16 downto 0);
> )
>       is
>  begin
>      x_sctrl  <= ctrl;
>      x_sprd   <= prd;
>      x_sht    <= ht;
>  end procedure;
>
> ...
>
> P_DATA(X"04", X"0009",X"000A",i_sctrl,i_sprd,i_sht);
>
> Duke

Hi Duke,

Thanks a lot. It's a exactly what I wanted to do. It works like a charm

Many Thanks

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig