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Forum: FPGA, VHDL & Verilog Procedure in VHDL testbench


von Bah (Guest)


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Hello there,

I am trying to implement a procedure in my testbench to shorten the 
lenght.
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entity tb is
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end entity;
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architecture sim of tb is
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  procedure P_DATA(
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      constant ctrl  : in std_logic_vector (8 downto 0);
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      constant ht    : in std_logic_vector (16 downto 0);
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      constant prd   : in std_logic_vector (16 downto 0))
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      is
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      variable i_sctrl  :  std_logic_vector (8 downto 0);
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      variable i_sprd    :  std_logic_vector (16 downto 0);
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      variable i_sht     :  std_logic_vector (16 downto 0);
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 begin
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     i_sctrl  := ctrl;
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     i_sprd   := prd;
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     i_sht    := ht;
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 end procedure;
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  signal i_clk   : std_logic;
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  signal i_rst   : std_logic; 
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  signal i_sctrl : std_logic_vector (8 downto 0);
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  signal i_sprd  : std_logic_vector (16 downto 0;
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  Signal i_sht   : std_logic_vector (16 downto 0;
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  ....
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begin
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  -- Data generation
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  pr_int : process
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  begin
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      i_rst <= '1';
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      i_sctrl <= (others => '0');
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      i_sprd  <= (others => '0');
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      i_sht   <= (others => '0');
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      wait for 5 ns;
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      i_rst <= '0';
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      wait for 2 ns;
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      wait for rising_edge(i_clk);
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      P_DATA(X"04", X"0009",X"000A");
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      wait for 1 ns;
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      wait;
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     end process;
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end architecture;

When I simulate to above Code my inputs data are all "zero" all the 
time. How can I modify the procedure to get the set values in the 
simulation waveform

Many thanks

von Duke Scarring (Guest)


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The signals i_sctrl, i_sprd and i_sht are in a diffrent scope, than the 
variables with the same name inside the procedure.

If you want zu use them, you have to add them to the parameter list:
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  procedure P_DATA(
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      constant ctrl  : in std_logic_vector (8 downto 0);
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      constant ht    : in std_logic_vector (16 downto 0);
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      constant prd   : in std_logic_vector (16 downto 0);
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      signal x_sctrl : out std_logic_vector (8 downto 0);
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      signal x_sprd  : out std_logic_vector (16 downto 0);
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      signal x_sht   : out std_logic_vector (16 downto 0);
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)
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      is
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 begin
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     x_sctrl  <= ctrl;
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     x_sprd   <= prd;
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     x_sht    <= ht;
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 end procedure;
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...
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P_DATA(X"04", X"0009",X"000A",i_sctrl,i_sprd,i_sht);

Duke

von Bah (Guest)


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Duke Scarring wrote:
> The signals i_sctrl, i_sprd and i_sht are in a diffrent scope,
> than the
> variables with the same name inside the procedure.
>
> If you want zu use them, you have to add them to the parameter list:
> procedure P_DATA(
>       constant ctrl  : in std_logic_vector (8 downto 0);
>       constant ht    : in std_logic_vector (16 downto 0);
>       constant prd   : in std_logic_vector (16 downto 0);
>       signal x_sctrl : out std_logic_vector (8 downto 0);
>       signal x_sprd  : out std_logic_vector (16 downto 0);
>       signal x_sht   : out std_logic_vector (16 downto 0);
> )
>       is
>  begin
>      x_sctrl  <= ctrl;
>      x_sprd   <= prd;
>      x_sht    <= ht;
>  end procedure;
>
> ...
>
> P_DATA(X"04", X"0009",X"000A",i_sctrl,i_sprd,i_sht);
>
> Duke

Hi Duke,

Thanks a lot. It's a exactly what I wanted to do. It works like a charm

Many Thanks

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