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Word Processing using verilog
von dayana42200 (Guest)

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Hi all.

Ive a stream of DNA sequence.

A G T G C T T G

and I want a output of

1
input   A G T G C T T C

2
outputs A G

3
        A G T

4
          G T G

5
            T G C

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              G C T

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                C T T

8
                  T T C

9
                    T C


For now what I think is to used Shift Register (Serial In Serial 
Out(SISO)). Below the the SISO and its testbench verilog code.

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module SISO (Clk, Load, SIn, SOut);

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  parameter PE = 3;

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  parameter QCbit = 3;

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   input  Clk, Load; 

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  input  [QCbit-1:0] SIn;

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   output [QCbit-1:0] SOut;

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   reg [(QCbit*PE)-1:0] sr ;            //3 x 3QC  = 24 bits

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  always@(posedge Clk)

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    begin

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      if (Load)                

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        begin

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          sr <= {sr[2:0], SIn};  //shift by 2 and concatenate Input

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        end

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      else             

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         begin

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          sr <= 1'd0;  

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         end

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    end

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assign SOut = sr[5:3];            // complete shiftreg is serially output

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endmodule

1
module SISO_tb();

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  /*parameter InWidth = 3;*/

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  localparam

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    N_A         = 3'b000,        //nucleotide "A"

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    N_C         = 3'b001,        //nucleotide "C"

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    N_G         = 3'b010,        //nucleotide "G"

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    N_T         = 3'b011;        //nucleotide "T"

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  reg            Clk,Load;

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  reg     [2:0]  SIn;

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  wire    [2:0]  SOut;

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initial

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  begin

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    Clk = 0;

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    forever

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      begin

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        Clk = 0; #20;

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        Clk = 1; #20;

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      end

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  end

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initial

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  begin

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    Load = 0; #10; 

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    Load = 1; #600; // 2*length of SISO

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    Load = 0; #10;

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  end

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initial

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  begin

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    SIn = N_A; #30; 

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    SIn = N_G; #40;

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    SIn = N_T; #40;

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    SIn = N_G; #40;

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    SIn = N_C; #40; 

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    SIn = N_T; #40;

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    SIn = N_T; #40;

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    SIn = N_C; #40;

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  end

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initial

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  begin

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    #700$finish;

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  end

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SISO SISO_inst(

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                .Clk      (Clk),

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    .Load     (Load),

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    .SIn      (SIn),

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    .SOut     (SOut)

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        );

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endmodule


Is it possible to produce that kind of word output using SISO?
Do you guys have idea?

  


  




  

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    Re: Word Processing using verilog
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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dayana42200 wrote:
> I want a output of
There is no clock or timing information in that picture. I don't get the 
trick. So some question remain:

> outputs A G
>         A G T
> ...
The output length is variable?

> Ive a stream of DNA sequence.
> A G T G C T T G
You get one "character" with each clock?

> Below the the SISO and its testbench verilog code.
Whats happening with thoe two in the simulator?
And whats wrong with that whats happening?
What do you expect and what do you get instead?

  


  



  

  
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    Edited by Moderator
  

  


  

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    Re: Word Processing using verilog
  


  

    

      von
      
        dayana42200 (Guest)
      
      


      
    


    

      
    

    

    

      

      

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Lothar M. wrote:

> There is no clock or timing information in that picture. I don't get the
> trick. So some question remain:
  I want the output in every clock cycle.

> The output length is variable?
  Yes as shown in the output pattern.

> You get one "character" with each clock?
  Yes as shown in the attached waveform.

> Whats happening with thoe two in the simulator?
> And whats wrong with that whats happening?
> What do you expect and what do you get instead?
As you can see, in the attached waveform, it is just a normal SISO that 
works. I expect the output pattern that I show and I have no idea how to 
process the DNA stream.

  


  




  

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