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Forum: FPGA, VHDL & Verilog Word Processing using verilog


Author: dayana42200 (Guest)
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Hi all.

Ive a stream of DNA sequence.

A G T G C T T G

and I want a output of
input   A G T G C T T C
outputs A G
        A G T
          G T G
            T G C
              G C T
                C T T
                  T T C
                    T C

For now what I think is to used Shift Register (Serial In Serial 
Out(SISO)). Below the the SISO and its testbench verilog code.
module SISO (Clk, Load, SIn, SOut);
 
  parameter PE = 3;
  parameter QCbit = 3;
  
   input  Clk, Load; 
  input  [QCbit-1:0] SIn;
   output [QCbit-1:0] SOut;

   reg [(QCbit*PE)-1:0] sr ;            //3 x 3QC  = 24 bits

  always@(posedge Clk)
    begin
      if (Load)                
        begin
          sr <= {sr[2:0], SIn};  //shift by 2 and concatenate Input
        end
      else             
         begin
          sr <= 1'd0;  
         end
    end
   
assign SOut = sr[5:3];            // complete shiftreg is serially output

endmodule
module SISO_tb();

  /*parameter InWidth = 3;*/

  localparam
    N_A         = 3'b000,        //nucleotide "A"
    N_C         = 3'b001,        //nucleotide "C"
    N_G         = 3'b010,        //nucleotide "G"
    N_T         = 3'b011;        //nucleotide "T"
  
  reg            Clk,Load;
  reg     [2:0]  SIn;
  wire    [2:0]  SOut;
  
initial
  begin
    Clk = 0;
    forever
      begin
        Clk = 0; #20;
        Clk = 1; #20;
      end
  end
  
initial
  begin
    Load = 0; #10; 
    Load = 1; #600; // 2*length of SISO
    Load = 0; #10;
  end
  
initial
  begin
    SIn = N_A; #30; 
    SIn = N_G; #40;
    SIn = N_T; #40;
    SIn = N_G; #40;
    SIn = N_C; #40; 
    SIn = N_T; #40;
    SIn = N_T; #40;
    SIn = N_C; #40;
  end
      
initial
  begin
    #700$finish;
  end

SISO SISO_inst(
                .Clk      (Clk),
    .Load     (Load),
    .SIn      (SIn),
    .SOut     (SOut)
        );

endmodule

Is it possible to produce that kind of word output using SISO?
Do you guys have idea?

Author: Lothar M. (lkmiller) (Moderator)
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dayana42200 wrote:
> I want a output of
There is no clock or timing information in that picture. I don't get the 
trick. So some question remain:

> outputs A G
>         A G T
> ...
The output length is variable?

> Ive a stream of DNA sequence.
> A G T G C T T G
You get one "character" with each clock?

> Below the the SISO and its testbench verilog code.
Whats happening with thoe two in the simulator?
And whats wrong with that whats happening?
What do you expect and what do you get instead?

: Edited by Moderator
Author: dayana42200 (Guest)
Posted on:
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Lothar M. wrote:

> There is no clock or timing information in that picture. I don't get the
> trick. So some question remain:
  I want the output in every clock cycle.

> The output length is variable?
  Yes as shown in the output pattern.

> You get one "character" with each clock?
  Yes as shown in the attached waveform.

> Whats happening with thoe two in the simulator?
> And whats wrong with that whats happening?
> What do you expect and what do you get instead?
As you can see, in the attached waveform, it is just a normal SISO that 
works. I expect the output pattern that I show and I have no idea how to 
process the DNA stream.

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