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wired_and , wired_or VHDL
von Aldemaro G. (aldemguz)

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Hi everyone!. In my project I have some moduls (each one has two outputs 
called calck_out(std_logic) and z_out (std_logic_vector(16bits)).

I need to leave only 1 module, just the one that will have clack_out = 
1.

I have readed abbout wired-and and wired-or but i don't understand that! 
:C

I should to use bus instead of signals?. hoy i can make it?

Please help me. if Somebody can explain me: wired-and and wired_or 
related wit my project at the same time, that will be very usefull.

Each one have clack_out and z_out. thanks a lot

1
component neurona

2
    Port ( x_in : in  STD_LOGIC_VECTOR (15 downto 0);

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           proto_in : in  STD_LOGIC_VECTOR (1 downto 0);

4
           izq_in : in  STD_LOGIC;

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        clack_in : in STD_LOGIC;

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        clack_history_in : in STD_LOGIC;

7
           clk : in  STD_LOGIC;

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           reset_in : in  STD_LOGIC;

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           rec_out : out  STD_LOGIC;

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           der_out : out  STD_LOGIC;

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        clack_out : out STD_LOGIC;

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        clack_history_out: out STD_LOGIC;

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        proto_out: out STD_LOGIC_VECTOR(1 downto 0);

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           z_out : out  STD_LOGIC_VECTOR (15 downto 0));

15
end component;

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Re: wired_and , wired_or VHDL
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Aldemaro G. wrote:
> Somebody can explain me: wired-and and wired_or related wit my project
First: forget about such a hardware specific detail like wired-and and 
wired-or. Just write the function in a way it is best readable and don't 
think about its implementation.

> at the same time, that will be very usefull.
Do you want that just for simulation? Or will it go into real hardware 
like a FPGA?

All in all: what is your actual problem? And why do you think the only 
way to solve it are those wired-and/wired-or?

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Re: wired_and , wired_or VHDL
von Aldemaro G. (aldemguz)

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> Do you want that just for simulation? Or will it go into real hardware
> like a FPGA?
 real hardware, just a FPGA.
> All in all: what is your actual problem? And why do you think the only
> way to solve it are those wired-and/wired-or?
the problem is:
I have n data, but i want to leave just 1. (like a multiplexor) but
I don't have a select signal, I need to detect wich one module have 
"clack" 1 and let it leave
I can create and decoder to do it. but is better to use wired-and or 
wired-or? I don't know.

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Re: wired_and , wired_or VHDL
von Theor (Guest)

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Its still open, for which reason you think, you must or shall use a 
wired-or or a wired-and.


If the "thing" shall output:

a) a one, if any of the inputs is one
and
b) a zero, if none of the inputs is one (in other words: each and every 
input is zero)

this perfectly matches the description of an OR-Gate.

So again: Why do you think, you shall use a wired-or?

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Re: wired_and , wired_or VHDL
von Dariusz Petrovski (Guest)

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Aldemaro G. wrote:
> I have readed abbout wired-and and wired-or but i don't understand that!

THERE IS NO WIRED AND OR WIRED OR IN FPGAs

THERE ARE ONLY WEIRED ANDS AND ORS PREDEFINED BY PERSONS HAVING HAD 
LEARNED VERILOG OR VHDL BY SELF STUDIES AND FACEBOOK AND HAVING REPOSTED 
THEIR WEIRED UNDERSTANDING REGARDING DIGITAL ELECTRONICS IN NEWSGROUPS 
TO SHOW OFF.

GO TO A UNIVERSITY AND LEARN ELECTRONICS FROM TEACHERS HAVING UNDERSTOOD 
DIGITAL DESIGN AND IGNORE THE BULL ALL AROUND.

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Re: wired_and , wired_or VHDL
von Aldemaro G. (aldemguz)

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I need that, for example.

let get out the data when clack is 1.

do i need to create a decoder?. I can resolve that with it. but it is 
the best? or is there a better solution?

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Re: wired_and , wired_or VHDL
von Aldemaro G. (aldemguz)

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> THERE IS NO WIRED AND OR WIRED OR IN FPGAs
thanks for this answer, I didn't know this.

> GO TO A UNIVERSITY AND LEARN ELECTRONICS FROM TEACHERS HAVING UNDERSTOOD
> DIGITAL DESIGN AND IGNORE THE BULL ALL AROUND.
ok well, Just a teacher recommended me use it, thanks for your advice. 
I'm sorry if I bothered you.

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Re: wired_and , wired_or VHDL
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Aldemaro G. wrote:
> Just a teacher recommended me use it, thanks for your advice.
How old is he/she?

Aldemaro G. wrote:
> let get out the data when clack is 1.
What "data"?
Is "z" the "data"?
And "c" should get that "z" from where "clack" is '1'?
And it is for sure that only 1 of theose "clack" are active at the very 
same time?

Then I would do it this way in VHDL:
1
   c <= az when aclack='1' else

2
        bz when bclack='1' else

3
        :

4
        ez when eclack='1' else

5
        fz;

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