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Verilog : postive Edge Trigger
von Saraswathy S. (saras015)

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I am generating Trigger Signal and counter data in single Verilog code.

Logic (verilog): 1. Generating Trigger Signal for 500ns -Output Port 
trig_out
                 2. Generating counter data (counter_result)
                 3. collecting and Storing counter data (Final_Value) at 
every Positive edge of trigger signal.

detect Port- Positive Edge detector of trigger signal.

Please debug my code. Because i am unable to collect the edge value 
(counter value) of Trigger signal.

1
module Counter_Design

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#(parameter N = 25)

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(

4
    input clk,

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    input rst,

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    input enable,

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  output reg[31:0] Final_value,

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    output reg trig_out

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    );

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reg [31:0]counter;

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reg [31:0] counter_result;

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reg temp1;

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wire detect;

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wire temp2;

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always @(posedge clk or posedge rst) begin

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  if (rst) begin

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    // reset

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    counter <= 0;

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  end

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  else if (counter == N-1) begin

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    counter <= 0;

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  end

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  else if (enable==1'b1)

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  begin

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    counter <= counter + 1;

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  end

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end

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always @(posedge clk or posedge rst) 

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begin

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  if (rst) begin

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    // reset

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    trig_out <= 0;

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  end

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  else if (counter == N-1) begin

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    trig_out <= !trig_out;

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  end

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end

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always @(posedge clk or posedge rst)  

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begin

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  if (rst) 

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  begin

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    // reset

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    trig_out <= 0;

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  end

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    else begin

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      temp1 <= trig_out;

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     end

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end

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assign detect=trig_out & ~temp1;

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 assign temp2=temp1&&clk;

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always @(posedge temp2 or posedge rst)  

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begin

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  if (rst) 

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  begin

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     counter_result<=0;   

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  end

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    else begin

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      counter_result<=counter_result+1;

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     end

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end

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always @(posedge detect or posedge rst) 

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 begin

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    if(rst)

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    begin

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    Final_value<=0; 

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    end

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    else if (counter == N-1) begin

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    Final_value<=counter_result;

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    end

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end

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endmodule


  


  




  

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    Re: Verilog : postive Edge Trigger
  


  

    

      von
      
        Duke Scarring (Guest)
      
      


      
    


    

      
    

    

    

      

      

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Saraswathy S. wrote:
> Please debug my code. Because i am unable to collect the edge value
> (counter value) of Trigger signal.

At first: Write a testbench, so that others can reproducible your 
problem:
1
module counter_tb;

2
    

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    // testbench signals

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    reg tb_clk;

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    reg tb_rst;

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    reg tb_enable;

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    wire [31:0] tb_final_value;

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    wire tb_trig_out;

9
10
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    // design under test

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    Counter_Design DUT (

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        .clk            ( tb_clk),

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        .rst            ( tb_rst),

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        .enable         ( tb_enable),

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        .Final_value    ( tb_final_value),

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        .trig_out       ( tb_trig_out)

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    );

19
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    // stimuli

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    initial

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    begin

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        tb_clk = 0;

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        tb_rst = 1;

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        tb_enable = 0;

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        # 7 tb_rst = 0;

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        # 55 tb_enable = 1;

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        # 99 tb_enable = 0;

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        # 135 tb_enable = 1;

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        # 1000 $finish;

31
    end

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    // clock generator

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    always

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        #5 tb_clk = ~tb_clk;

36
37
endmodule


I attached a slightly modified version of your code, which update 
Final_value when the counter is reseted. Maybe I didn't understand you 
correctly with you problem.

Duke

  


  




  

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    Re: Verilog : postive Edge Trigger
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Saraswathy S. wrote:
> Because i am unable to collect the edge value (counter value) of Trigger
> signal.
You are generating that value. So it should be very easy to do any 
processing there.

> assign temp2=temp1&&clk;
> always @(posedge temp2 or posedge rst)
It is no good design practice to use gated clocks. Absolutely not! A 
hint for the beginner: use only 1 clock in the whole FPGA and do all 
enabling inside the clock processing, somewhat like this:
1
always @(posedge clk or posedge rst)  

2
begin

3
  if (rst) 

4
  begin

5
     counter_result<=0;   

6
  end

7
    else begin

8
      // do the clock-enabling here

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      if (clock_enable)

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         counter_result<=counter_result+1;

11
      end 

12
     end

13
end


> always @(posedge detect
It is no good design practice to use any random input as a clock source. 
Treat that "detect" signal as a simple input and synchronize it to the 
OneAndOnly-FPGA-Clock. Then store it in two flipflops one after the 
other and compare the values of those two flipflops to detect an edge of 
that input signal. This is called synchronous design. And thats the only 
thing that works reliably in the real world...

Saraswathy S. wrote:
> Please debug my code.
Whats the problem with it?

> Because i am unable to collect the edge value of Trigger signal.
How did you find that out? What do you expect of that code? And what do 
you get instead?
Where in your description is a repetition of the Trigger Signal? I can't 
find no one.

Saraswathy S. wrote:
> 1. Generating Trigger Signal for 500ns -Output Port trig_out
So only one Trigger pulse must be generated.
> 2. Generating counter data (counter_result)
From what? When should the counter stop?
> 3. collecting and Storing counter data (Final_Value) at every Positive
> edge of trigger signal.
According to 1. there is only 1 Trigger Signal active once for 500ns.
Shoul the trigger start later on once more? After a certain time? Or a 
certain event?

Can you draw a sketch of that timing of those few signals and the 
desired reaction?

  


  



  

  
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