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Forum: FPGA, VHDL & Verilog I don't understand this


Author: Aldemaro G. (aldemguz)
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Hello everyone!. I have a problem!. I can't understand why do not work 
how i hope it..

I have 2 components "registro_16bits" and "decoEstado"

on Registro_16bits:
when rising_edge of clock and enable is 1: I can write on Z_out the X_in 
value; I don't have problem here.

the problem is when I connect decoEstado with registro_16bits.

decoEstado receives izq_in and der_in.
truth table:
izq_in | der_in  | z_out
     0          0      0
     0          1      0
     1          0      1
     1          1      0

my desing should to work:
when izq_in is 1 and der_in is 0 I should save x_in value and let get 
out that value on z_out.

 I use decoEstado to assign enable_in on registro_16bits.

I'm apologize, but i don't speak english very well.. I hope u can help 
me..
thanks


I attach the whole code and 2 TestBench Pictures!

---------------------------------------------------------------

-- Registro_16bits code
entity registro_16bits is
    Port ( x_in : in  STD_LOGIC_VECTOR (15 downto 0);
           enable_in : in  STD_LOGIC;
           reset_in : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           z_out : out  STD_LOGIC_VECTOR (15 downto 0));
end registro_16bits;

architecture Behavioral of registro_16bits is
--signal temp: std_logic_vector(15 downto 0):=(others=>'0');
begin

process(clk,reset_in)
begin
if reset_in='1' then
  z_out<="0000000000000000";
  elsif(clk'event and clk='1') then
  if(enable_in='1') then
  z_out<=x_in;
  end if;
end if;
end process;

end Behavioral;
----------------------------------------------------------
----------------------------------------------------------
--deEstado Code
entity decoEstado is
    Port ( izq_in : in  STD_LOGIC;
           der_in : in  STD_LOGIC;
           z_out : out  STD_LOGIC);
end decoEstado;

architecture Behavioral of decoEstado is

begin

z_out<= izq_in and not(der_in);
end Behavioral;

--------------------------------------------------------
--------------------------------------------------------
-- neurona_simple code


entity neurona_simple is
    Port ( x_in : in  STD_LOGIC_VECTOR (15 downto 0);
           izq_in : in  STD_LOGIC;
           der_in : in  STD_LOGIC;
           reset_in : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           z_out : out  STD_LOGIC_VECTOR (15 downto 0));
end neurona_simple;

architecture Behavioral of neurona_simple is

component registro_16bits
    Port ( x_in : in  STD_LOGIC_VECTOR (15 downto 0);
           enable_in : in  STD_LOGIC;
           reset_in : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           z_out : out  STD_LOGIC_VECTOR (15 downto 0));
end component;

component decoEstado is
    Port ( izq_in : in  STD_LOGIC;
           der_in : in  STD_LOGIC;
           z_out : out  STD_LOGIC);
end component;

signal enable_sg : std_logic :='0';
begin

deco : decoEstado port map(izq_in,der_in,enable_sg);
reg : registro_16bits port map(x_in,enable_sg,reset_in,clk,z_out);

end Behavioral;
----------------------------------------------------------------------

Author: Aldemaro G. (aldemguz)
Posted on:

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I want to know why don't save the value "2" when the registro_16bits 
receives enable_in = 1 and x_in = 2 on neurona_simple's testbench. I've 
tested that on registro_16bits and all be ok!.

Author: Lothar M. (lkmiller) (Moderator)
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Congratiulations, you found the thing called "latency".

Aldemaro G. wrote:
> when the registro_16bits receives enable_in = 1 and x_in = 2 on
> neurona_simple's testbench.
On (or better before!) the rising egde of "clk" the "enable_in" is '0' 
and therefore "z_out" isn't changed. You see the very same behaviour at 
the moment, when the value '4' doesn't appear on "z_out".

BTW: why so much modules and wiring for a thing you could write in 
almost one line?
entity neurona_simple is
    Port ( x_in : in  STD_LOGIC_VECTOR (15 downto 0);
           izq_in : in  STD_LOGIC;
           der_in : in  STD_LOGIC;
           reset_in : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           z_out : out  STD_LOGIC_VECTOR (15 downto 0));
end neurona_simple;

architecture Behavioral of neurona_simple is

signal enable_sg : std_logic :='0';
begin

  z_out <= (others=>'0') when reset_in='1'   else 
           x_in when rising_edge(clk) and izq_in and not(der_in);

end Behavioral;

: Edited by Moderator
Author: Aldemaro G. (aldemguz)
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> Congratiulations, you found the thing called "latency".

Thnks for the answer, but how can i calculate it?(can u recommend me a 
book?) Because when i see both testbench, I think those (tb) receives 
the same when rising_edge, :c

Author: Aldemaro G. (aldemguz)
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> BTW: why so much modules and wiring for a thing you could write in
> almost one line?entity neurona_simple is

I had thinked that. trust me.. but i want to know why don't they behave 
same.. if i want to be a "good designer" into VHDL. i must to know the 
difference between both. And how i can resolve it. I'm crazy.. i know 
^^u

Author: Lothar M. (lkmiller) (Moderator)
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Aldemaro G. wrote:
> but i want to know why don't they behave same..
What doesn't behave the same?
My description of course behave like yours. I just wanted to show how to 
shorten your nearly hundred lines of code down to one line...

> And how i can resolve it.
You must assign the values to "izq_in" and "der_in" well before the 
next rising edge of "clk".
Or you must start to find the trick behind that "latency": at the rising 
edge of the "clk" the registers attached to it take the values that you 
see just before that edge. And if the enable signals are inactive just 
before the "clk" then the registers won't change at all. Thats what you 
see with your code, and thats the same with my code.

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