Hello everyone!. I have a problem!. I can't understand why do not work
how i hope it..
I have 2 components "registro_16bits" and "decoEstado"
on Registro_16bits:
when rising_edge of clock and enable is 1: I can write on Z_out the X_in
value; I don't have problem here.
the problem is when I connect decoEstado with registro_16bits.
decoEstado receives izq_in and der_in.
truth table:
izq_in | der_in | z_out
0 0 0
0 1 0
1 0 1
1 1 0
my desing should to work:
when izq_in is 1 and der_in is 0 I should save x_in value and let get
out that value on z_out.
I use decoEstado to assign enable_in on registro_16bits.
I'm apologize, but i don't speak english very well.. I hope u can help
me..
thanks
I attach the whole code and 2 TestBench Pictures!
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-- Registro_16bits code
1 | entity registro_16bits is
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2 | Port ( x_in : in STD_LOGIC_VECTOR (15 downto 0);
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3 | enable_in : in STD_LOGIC;
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4 | reset_in : in STD_LOGIC;
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5 | clk : in STD_LOGIC;
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6 | z_out : out STD_LOGIC_VECTOR (15 downto 0));
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7 | end registro_16bits;
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8 |
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9 | architecture Behavioral of registro_16bits is
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10 | --signal temp: std_logic_vector(15 downto 0):=(others=>'0');
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11 | begin
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12 |
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13 | process(clk,reset_in)
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14 | begin
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15 | if reset_in='1' then
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16 | z_out<="0000000000000000";
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17 | elsif(clk'event and clk='1') then
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18 | if(enable_in='1') then
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19 | z_out<=x_in;
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20 | end if;
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21 | end if;
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22 | end process;
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23 |
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24 | end Behavioral;
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----------------------------------------------------------
----------------------------------------------------------
--deEstado Code
1 | entity decoEstado is
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2 | Port ( izq_in : in STD_LOGIC;
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3 | der_in : in STD_LOGIC;
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4 | z_out : out STD_LOGIC);
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5 | end decoEstado;
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6 |
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7 | architecture Behavioral of decoEstado is
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8 |
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9 | begin
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10 |
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11 | z_out<= izq_in and not(der_in);
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12 | end Behavioral;
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--------------------------------------------------------
--------------------------------------------------------
1 | -- neurona_simple code
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2 |
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3 |
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4 | entity neurona_simple is
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5 | Port ( x_in : in STD_LOGIC_VECTOR (15 downto 0);
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6 | izq_in : in STD_LOGIC;
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7 | der_in : in STD_LOGIC;
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8 | reset_in : in STD_LOGIC;
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9 | clk : in STD_LOGIC;
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10 | z_out : out STD_LOGIC_VECTOR (15 downto 0));
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11 | end neurona_simple;
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12 |
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13 | architecture Behavioral of neurona_simple is
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14 |
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15 | component registro_16bits
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16 | Port ( x_in : in STD_LOGIC_VECTOR (15 downto 0);
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17 | enable_in : in STD_LOGIC;
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18 | reset_in : in STD_LOGIC;
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19 | clk : in STD_LOGIC;
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20 | z_out : out STD_LOGIC_VECTOR (15 downto 0));
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21 | end component;
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22 |
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23 | component decoEstado is
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24 | Port ( izq_in : in STD_LOGIC;
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25 | der_in : in STD_LOGIC;
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26 | z_out : out STD_LOGIC);
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27 | end component;
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28 |
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29 | signal enable_sg : std_logic :='0';
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30 | begin
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31 |
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32 | deco : decoEstado port map(izq_in,der_in,enable_sg);
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33 | reg : registro_16bits port map(x_in,enable_sg,reset_in,clk,z_out);
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34 |
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35 | end Behavioral;
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