I am working on the integration of Lattice semiconductor IPs for image 
fusion.
I block in the map design stage ,I get this error:

ERROR - Design is empty.

I do not know the cause of this error , can someone help me please.

The typical reason for this is unconnected clock, permanently assigned 
reset, unconnected input or output ports.

Thank you for your answers
I checked and found warnings like that :

port XXX remains unconnected for this instance.


I guess it is due to some ports that are not connected as you said.
I got rid of all warnings but I still have this one :

WARNING - C:/Users/Mesotic/Desktop/Fusion/csi2_2_csi2_ip.v(509,1-568,3) 
(VERI-1927) port d1_p_i remains unconnected for this instance

d1_p_i is an inout port which is declared in DPHY_2_CMOS module.
I instantiated the DPHY_2_CMOS module in an other module which is called 
csi_2_csi.
This is the instantiation and d1_p_i is connected to d1_ch1_p_i :
dphy_2_cmos_ip dphy2cmos_ch1 (
        .reset_n_i (reset_n_i),
        .reset_byte_n_i (reset_n_i),
          .reset_byte_fr_n_i (reset_byte_fr_n_i),
        .reset_lp_n_i (reset_lp_n_i),
        .clk_lp_ctrl_i (clk_lp_ctrl_i),
        .clk_pixel_i (1'b0),
        .pll_lock_i (tx_pll_lock),
        .lp_d0_tx_en_i (1'b0),
        .lp_d0_tx_n_i (1'b0),
        .lp_d0_tx_p_i (1'b0),
        .reset_pixel_n_i (1'b0),
      `ifdef RX_CLK_MODE_HS_LP
        .clk_byte_fr_i (rx_byte_clk_fr_ch1),
      `elsif RX_CLK_MODE_HS_ONLY
        .clk_byte_fr_i (rx_byte_clk_fr_ch1),
        .clk_byte_fr_o (rx_byte_clk_fr_ch1),
      `endif
        .clk_p_i (clk_ch1_p_i),
        .clk_n_i (clk_ch1_n_i),
      `ifdef NO_OF_LANE_1
        .d0_p_i (d0_ch1_p_i),
        .d0_n_i (d0_ch1_n_i),
        .bd_o (ch1_byte_data0),
            `elsif NO_OF_LANE_2
        .d0_p_i (d0_ch1_p_i),
        .d0_n_i (d0_ch1_n_i),
        .d1_p_i (d1_ch1_p_i),
        .d1_n_i (d1_ch1_n_i),
        .bd_o ({ch1_byte_data1,ch1_byte_data0}),
      `elsif NO_OF_LANE_4
        .d0_p_i (d0_ch1_p_i),
        .d0_n_i (d0_ch1_n_i),
        .d1_p_i (d1_ch1_p_i),
        .d1_n_i (d1_ch1_n_i),
        .d2_p_i (d2_ch1_p_i),
        .d2_n_i (d2_ch1_n_i),
        .d3_p_i (d3_ch1_p_i),
        .d3_n_i (d3_ch1_n_i),
        .bd_o 
({ch1_byte_data3,ch1_byte_data2,ch1_byte_data1,ch1_byte_data0}),
      `endif
        .lv_o (),
        .fv_o (),
        .wc_o(wc_ch1),
      `ifdef LR
        .vc_o(vc_ch1),
      `endif
      // debug pins
        .lp_en_o (lp_en_ch1),
        .sp_en_o (sp_en_ch1),
        .dt_o (dt_ch1),
                                .payload_en_o(d2c_payload_en_ch1),
        //.hs_en_o (hs_en_ch1),
        .hs_sync_o (hs_sync_ch1),
        .lp_hs_state_d_o (lp_hs_state_ch1),
        .d0_p_io (),
        .d0_n_io ()


);

I don't now how to resolve it.
Thank you beforehand.