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Forum: FPGA, VHDL & Verilog Conceptual help needed


Conceptual help needed
von Mike P. (mprsvn)

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Dear colleagues,

I have come to a point, where FPGA is required in the design. I have 
flashed the LED, implemented 8 segment indicator, button debouncing and 
other trivial stuff. But I don't see the whole picture yet, and will 
appreciate any advice on how to approach the problem.

Problem statement:

1) FPGA board should read data from a 12 bit 8 channel simultaneously 
sampled ADC at 500 KSPS for each channel, connected via parallel 
interface.
2) Sampling happens during 45 ms, followed by 15 ms pause.
3) Running average is calculated for the measured vector.
4) The vector is logarithmically binned into a smaller 30 point vector
5) 30 point vector is sent to external world.

Questions:
Provided, that the hardware is working,

1) can I estimate which model (logic cells, speed grade, etc is needed) 
before I implement the design?
2) Is Nios II needed or can it simplify the development?
3) What difficulties can I encounter using the external RAM chip? 
(provided hardware is working)
4) Very roughly how much man-hours are needed to implement the project 
if a person is proficient in the HDL?
5) How should I approach floating point arithmetic?
6) Am I missing some key questions? :)

Thank you in advance,
M.

: Edited by User
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Re: Conceptual help needed
von Vancouver (Guest)

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Mike P. wrote:
> 1) can I estimate which model (logic cells, speed grade, etc is needed)
> before I implement the design?

Roughly. Make a system concept, try to estimate the number of registers 
in each toplevel block, identify the highest clock rate in your design.

> 2) Is Nios II needed or can it simplify the development?

Presumably not here. Sounds like typical streaming signal processing. 
But maybe a CPU core can help if you need some complex communication 
protocol stack (like TCP/IP) for the interface.

> 3) What difficulties can I encounter using the external RAM chip?
> (provided hardware is working)

Complex memory controller (e.g. for DDR) may increase the resource 
usage. For SRAM its quite simple. Why do you expect to use external 
memory at all?

> 4) Very roughly how much man-hours are needed to implement the project
> if a person is proficient in the HDL?

Depends on the interface, the timing requirements, the level of 
verification (just simulation of most common corner cases or water-proof 
formal verification). Between 3 weeks and 6 months everything is 
possible.

> 5) How should I approach floating point arithmetic?

You shouldn't. Fixpoint is sufficient for a sliding average. If you 
really need float, add some months to the worst case man-hours.

> 6) Am I missing some key questions? :)

Yes. You will identify them while making the concept and digging into 
the details. Key questions are always missing.

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