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Forum: FPGA, VHDL & Verilog Import package error system Verilog


Author: Nikhil Ghanathe (Guest)
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Hello,
I have a few packages that I have written like this:
package A; 
-- 
-- 
endpackage 

package B; 
import A::* 
--- 
-- 
endpackage 

package C; 
import A::*; 
import B::*; 
endpackage 
In the file using package C, the error I am getting is as follows:
Error (10864): SystemVerilog error at C.sv(26): TMP was imported from 
multiple packages with ::* - none of the imported declarations are 
visible.

Is this problem because I am importing A::* in both package A and 
package C?
Any help to rsolve this is greatly appreciated.

Thanks in Advance~

--
Nikhil Pratap

Author: Duke Scarring (Guest)
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Nikhil Ghanathe wrote:
> TMP was imported from
> multiple packages with
I think not A is the problem but TMP is imported multiple times.
Maybe you can import more selective with:
import A::special_only; 

Duke

Author: Nikhil G. (Company: Microsoft) (nikhilghanathe)
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Thanks Duke,
Will try that out.
A follow up question, is there like a guard statement (like `ifndef...) 
which can be used here to avoid importing multiple times?\

--
Nikhil Pratap

Author: Tom T. (gogul)
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Yes, same syntax as in C

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