Import package error system Verilog

Hello,
I have a few packages that I have written like this:

1

package A; 

2

-- 

3

-- 

4

endpackage 

5

6

package B; 

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import A::* 

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--- 

9

-- 

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endpackage 

11

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package C; 

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import A::*; 

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import B::*; 

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endpackage

In the file using package C, the error I am getting is as follows:
Error (10864): SystemVerilog error at C.sv(26): TMP was imported from 
multiple packages with ::* - none of the imported declarations are 
visible.

Is this problem because I am importing A::* in both package A and 
package C?
Any help to rsolve this is greatly appreciated.

Thanks in Advance~

--
Nikhil Pratap