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Forum: FPGA, VHDL & Verilog Import package error system Verilog

von Nikhil Ghanathe (Guest)

2018-09-07 11:02

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Hello,
I have a few packages that I have written like this:

package A; 
endpackage 
package B; 
import A::* 
endpackage 
package C; 
import A::*; 
import B::*; 
endpackage

In the file using package C, the error I am getting is as follows:
Error (10864): SystemVerilog error at C.sv(26): TMP was imported from 
multiple packages with ::* - none of the imported declarations are 
visible.

Is this problem because I am importing A::* in both package A and 
package C?
Any help to rsolve this is greatly appreciated.

Thanks in Advance~

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Nikhil Pratap

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Re: Import package error system Verilog

von Duke Scarring (Guest)

2018-09-07 12:31

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Nikhil Ghanathe wrote:
> TMP was imported from
> multiple packages with
I think not A is the problem but TMP is imported multiple times.
Maybe you can import more selective with:

import A::special_only;


Duke

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Re: Import package error system Verilog

von Nikhil G. (Company: Microsoft) (nikhilghanathe)

2018-09-07 13:36

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Thanks Duke,
Will try that out.
A follow up question, is there like a guard statement (like `ifndef...) 
which can be used here to avoid importing multiple times?\

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Nikhil Pratap

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Re: Import package error system Verilog

von Tom T. (gogul)

2018-09-10 08:04

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