EmbDev.net

Forum: FPGA, VHDL & Verilog More toggles than expected.


Author: bob (Guest)
Posted on:

Rate this post
0 useful
not useful
I have a process in my VHDL code that I want to advance a counter on a 
rising edge if an input(GPIO_READDATA(6) an encoder output much slower 
than 50 MHz. All entities are std_logic. cntr[32] and READ_DATA[7]are 
vectors.

My code is as follows:

  Catch_Rising_Edge: process(CLK)
  begin

  if rising_edge(CLK) then -- 50MHz clk
    r0_input <= GPIO_READDATA(6); --reading GPIO_READDATA(6)
    r1_input <= r0_input;
    ENC(1) <= GPIO_READDATA(6); -- ENC(1) drives a single LED

    if  (r1_input <= '0') and (r0_input <= '1')then
      cntr <= cntr+ 1; -- cntr(22 downto 15) drives a string of 8 LEDs

    end if;
  end if;

  end process;
My understanding is on a rising CLK, the first 4 lines occur 
simultaneously. The 5th line being a condition of the 4th also should 
occur simultaneously.
On the rising edge transition of GPIO_READDATA(6), r0 goes to '1' and r1 
stays at '0' because it reads r1 before r0 transitions. In the start of 
the next CLK cycle, r0 = '1' and r1 = '0' so the cntr advances.
However, that is not what is happening. When ENC(1) is low, cntr(22) is 
flashing at about 1 Hz making my cntr count at 50MHz. When ENC(1) is 
high, cntr stops. I am trying to understand ModelSim to further solve 
the issue. Please help me find the error in my code.

Thank you

Author: spongebob (Guest)
Posted on:

Rate this post
0 useful
not useful
if rising_edge(CLK) then
 if rising_edge(GPIO_READDATA(6)) then
  cntr <= cntr+ 1;
 end if;
end if;

thats all folks

Author: bob (Guest)
Posted on:

Rate this post
0 useful
not useful
I just tried that and it I cannot get it to work.
Catch_Rising_Edge: process(CLK, GPIO_READDATA(6))
  begin

  if rising_edge(CLK) then
    if rising_edge(GPIO_READDATA(6)) then
      cntr <= cntr+ 1;
      ENC(1) <= GPIO_READDATA(6);
    end if;
  end if;

  end process;
I get ... can't infer register for "cntr[1]" because its behavior does 
not match any supported register model

I also get 21 other similar errors.
I am a novice and was told to only implicitly trigger on a clock edge. 
What am I missing?

Author: bob (Guest)
Posted on:

Rate this post
0 useful
not useful
After taking a break, I saw the issue. I was using "<=" instead of "=".

Author: Lothar M. (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
bob wrote:
if rising_edge(CLK) then
  if rising_edge(GPIO_READDATA(6)) then
    cntr <= cntr+ 1;
  end if;
end if;
> I get ... can't infer register for "cntr[1]" because its behavior does
> not match any supported register model
Just to clarify the issues here:
Of course this code is not synthesizeable, because
1. it requires the cntr to be built with never seen "dual clock input 
flipflops" and
2. in real life there are no edges at the very same time as this code 
demands...

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig