I have a process in my VHDL code that I want to advance a counter on a 
rising edge if an input(GPIO_READDATA(6) an encoder output much slower 
than 50 MHz. All entities are std_logic. cntr[32] and READ_DATA[7]are 
vectors.

My code is as follows:

  Catch_Rising_Edge: process(CLK)
  begin

  if rising_edge(CLK) then -- 50MHz clk
    r0_input <= GPIO_READDATA(6); --reading GPIO_READDATA(6)
    r1_input <= r0_input;
    ENC(1) <= GPIO_READDATA(6); -- ENC(1) drives a single LED

    if  (r1_input <= '0') and (r0_input <= '1')then
      cntr <= cntr+ 1; -- cntr(22 downto 15) drives a string of 8 LEDs

    end if;
  end if;

  end process;
My understanding is on a rising CLK, the first 4 lines occur 
simultaneously. The 5th line being a condition of the 4th also should 
occur simultaneously.
On the rising edge transition of GPIO_READDATA(6), r0 goes to '1' and r1 
stays at '0' because it reads r1 before r0 transitions. In the start of 
the next CLK cycle, r0 = '1' and r1 = '0' so the cntr advances.
However, that is not what is happening. When ENC(1) is low, cntr(22) is 
flashing at about 1 Hz making my cntr count at 50MHz. When ENC(1) is 
high, cntr stops. I am trying to understand ModelSim to further solve 
the issue. Please help me find the error in my code.

Thank you