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Forum: FPGA, VHDL & Verilog Interface DHT22 to FPGA

von Bùi C. (Company: HUST) (skyfall_133)

2018-05-19 11:36

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Hi everyone.
Now, i make a circuit to get a temperature and humidity via DHT22 on 
FPGA. But when i test my testbench on my board(Elbert V2). it doesnt to 
run
 singer_bus right, . Any suggestions for me ?

(---------------------This is my 
code-------------------------------------)
------------------------------------------------------------------------ 
----------
-- Company:
-- Engineer:
--
-- Create Date:    16:00:25 05/09/2018
-- Design Name:
-- Module Name:    DHT11 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
------------------------------------------------------------------------ 
----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DHT11 is
  generic (
    CLK_PERIOD_NS : positive := 83;    -- 12MHz
  N: positive:= 40);
  port(
    clk,rst : in std_logic ;
--    en  : in std_logic ;
    singer_bus: inout std_logic;
    dataout: out std_logic_vector (N-1 downto 0);
    tick_done: out std_logic
  );
end DHT11;

architecture Behavioral of DHT11 is

  constant DELAY_1_MS: positive := 1*10**6/CLK_PERIOD_NS+1;
  constant DELAY_40_US: positive := 40*10**3/CLK_PERIOD_NS+1;
  constant DELAY_80_US: positive := 80*10**3/CLK_PERIOD_NS+1;
  constant DELAY_50_US: positive := 50*10**3/CLK_PERIOD_NS+1;
  constant TIME_70_US: positive := 80*10**3/CLK_PERIOD_NS+1; --bit  > 70 
us
  constant TIME_28_uS: positive := 30*10**3/CLK_PERIOD_NS+1; -- bit 0 > 
28 us
  constant MAX_DELAY  : positive := 5*10**6/CLK_PERIOD_NS+1; -- 5 ms

  type state_type is 
(reset,start_m,wait_res_sl,response_sl,delay_sl,start_sl,consider_logic, 
end_sl);

  signal  index, next_index : natural range 0 to MAX_DELAY;
  --signal  counter, next_counter: natural range 0 to MAX_DELAY;
  signal  state, next_state : state_type;
  signal   data_out,next_data_out: std_logic_vector (N-1 downto 0);
  signal   bit_in, next_bit_in: std_logic;
  signal  number_bit,next_number_bit: natural range 0 to 40;
  signal   oe: std_logic;

begin
  --register
  regis_state:process (clk,rst) begin
    if rst = '1' then
      state <= reset;
      index <= MAX_DELAY;
      number_bit <= 0;
      bit_in <= '1';
      data_out <= (others => '0');
    elsif rising_edge(clk) then
      state <= next_state;
      index <= next_index;
      number_bit <= next_number_bit;
      bit_in     <= next_bit_in;
      data_out   <= next_data_out;
    end if;
  end process regis_state;
  proces_state: process 
(singer_bus,index,state,bit_in,number_bit,data_out) begin
    tick_done <= '0';
    next_data_out <= data_out;
    next_number_bit <= number_bit;
    next_state <= state;
    next_data_out <= data_out;
    next_index <= index;
    dataout <= (others => '0');
    oe <= '0';
    next_bit_in <= bit_in;
    case(state) is
      when reset =>   -- initial

        if index = 0 then
          next_state <= start_m;
          next_index <= DELAY_1_MS;
          next_number_bit <= N-1;
        else
          next_state <= reset;
          next_index <= index - 1;
        end if;

      when start_m =>  -- master send '1' in 1ms
        if index = 0 then
          next_state <= wait_res_sl;
          next_index <= DELAY_40_US;
        else
          oe <= '1';
          next_state <= start_m;
          next_index <= index -1;
        end if ;
      when wait_res_sl => -- wait for slave response in 40us  -- xem xet 
th slave tac dong bat cu luc nao
        next_bit_in <= singer_bus;
        if  bit_in ='1' and next_bit_in = '0' then  --
          next_state <= response_sl;
        else
          next_state <= wait_res_sl;
        end if;
      when response_sl => -- slave response in 80us
        next_bit_in <= singer_bus;
        if bit_in ='0' and next_bit_in = '1' then
          next_state <= delay_sl;
        else
          next_state <= response_sl;
        end if;
      when delay_sl => -- wait for slave delay in 80us
        if bit_in = '1' and next_bit_in ='0' then
          next_state <= start_sl;
        else
          next_state <= delay_sl;
        end if;
      when start_sl => -- start to prepare in 50us
        if (bit_in = '0') and (next_bit_in = '1') then
          next_state <= consider_logic;
          next_index <= 0;
        elsif number_bit = 0 then
            next_state <= end_sl;
            next_index <= DELAY_50_US;
          else
            next_state <= start_sl;
        end if;
      when consider_logic => -- determine 1 bit-data of slave
        next_index <= index + 1;
        next_bit_in <= singer_bus;
        if bit_in = '1' and next_bit_in = '0' then -- the end of logic 
state
          next_number_bit <= number_bit -1;

          if (index < TIME_28_uS) then
            next_data_out <= data_out(N-2 downto 0) & '0';
          elsif (index < TIME_70_US) then
            next_data_out <= data_out(N-2 downto 0) & '1';
          end if;
            next_state <= start_sl;
            next_index <= DELAY_50_US;
        elsif bit_in ='1' and next_bit_in ='1' then
          next_state <= consider_logic;
        end if;
      when end_sl => --
        if index = 0 then
          next_index <= MAX_DELAY;
          next_state <= reset;
        else
          tick_done <= '1';
          dataout <= data_out;
          next_index <= index -1;
          next_state <= end_sl;
        end if;
    end case;
  end process proces_state;
  singer_bus <= '0' when oe ='1' else 'Z';
end Behavioral;


(------------------------------This is my 
testbench----------------------)
------------------------------------------------------------------------ 
--------
-- Company:
-- Engineer:
--
-- Create Date:   08:16:06 05/18/2018
-- Design Name:
-- Module Name:   E:/Work/HUST 20172/VHDL/Final term/1 
wire/one_wire_v2/one_wire_v2_tb.vhd
-- Project Name:  one_wire_v2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DHT11
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic 
and
-- std_logic_vector for the ports of the unit under test.  Xilinx 
recommends
-- that these types always be used for the top-level I/O of a design in 
order
-- to guarantee that the testbench will bind correctly to the 
post-implementation
-- simulation model.
------------------------------------------------------------------------ 
--------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY one_wire_v2_tb IS
END one_wire_v2_tb;

ARCHITECTURE behavior OF one_wire_v2_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DHT11
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         singer_bus : INOUT  std_logic;
         dataout : OUT  std_logic_vector(39 downto 0);
         tick_done : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --BiDirs
   signal singer_bus : std_logic;

   --Outputs
   signal dataout : std_logic_vector(39 downto 0);
   signal tick_done : std_logic;

   -- Clock period definitions
   constant clk_period : time := 83.33333333 ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)
   uut: DHT11 PORT MAP (
          clk => clk,
          rst => rst,
          singer_bus => singer_bus,
          dataout => dataout,
          tick_done => tick_done
        );

   -- Clock process definitions
   clk_process :process
   begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
    rst <= '1';
    wait for 100 us ;
    rst <= '0';
--    singer_bus <= '1'; -- intial
    wait for 60 ms;
    -- singer_bus <= '0'; -- master send
    -- wait for 1 ms;

    singer_bus <= '1'; -- wait response for slave
    wait for 40 us;
    singer_bus <= '0'; -- slave pull low
    wait for 80 us;
    singer_bus <= '1'; -- slave pull up
    wait for 80 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;


    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;

    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '1';
    wait for 68 us;
    singer_bus <= '0';  -- slave start data transmission
    wait for 50 us;
    singer_bus <= '1';  -- slave send bit '0';
    wait for 24 us;
    singer_bus <= '0';
    wait ;

   end process;

END;

2018-05-19 11:39: Edited by User

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Re: Interface DHT22 to FPGA

von Lothar M. (lkmiller) (Moderator)

2018-05-19 11:50

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Bùi C. wrote:
> Any suggestions for me ?
Real the few lines above each editbox here in teh forum! Here an 
excerpt:

Rules — please read before posting
    Post long source code as attachment, not in the text
Formatting options
    [vhdl]VHDL code[/vhdl]

Do the first, attach those files as *.vhdl files.

And then tell waht you expect and whatt happens instead?

2018-05-19 17:30: Edited by Moderator

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Re: Interface DHT22 to FPGA

von Bùi C. (Company: HUST) (skyfall_133)

2018-05-19 17:18

Attached files:

DHT11.vhd (5.99 KB, 346 downloads) | highlighted code
dht2_tb.vhd (25.1 KB, 265 downloads) | highlighted code

Capture1.JPG
114 KB, 343 downloads

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Sorry, this is my code and my testbench. In my code, i only set 
singer_bus = 'Z' or '1' but when i simulate it, singer_bus = 'U' and /= 
'Z'. Any suggestions for me? thank y0u. (you can see my imagine)

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Re: Interface DHT22 to FPGA

von Lothar M. (lkmiller) (Moderator)

2018-05-19 17:44

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'U' means "Uninitialized". You should initialize your signal in the test 
bench. Try that:    signal singer_bus : std_logic :='Z';

I can see some severe design flaws in your design!
All of them look like this:

        if singer_bus ='0' and reg_singer_bus = '1' then 
            next_state <= response_sl;
        else

Never ever use an asynchronous input signal in a FSM (and most signals 
end up in FSM) without synchronizing it with at least 1 or 2 flipflops!
Otherwise you will encounter something like this:
http://www.lothar-miller.de/s9y/archives/64-State-Machine-mit-asynchronem-Eingang.html
Its German, try google translator ;-)

When you don't sync the signal to the FPGAs clock domain you will have 
strange behaviour like wrong transitions now and then. "Now and then" 
may be "once a month" or "every few seconds"...

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Re: Interface DHT22 to FPGA

von Bùi C. (Company: HUST) (skyfall_133)

2018-05-21 08:16

Attached files:

one_wire_v2.vhd (5.2 KB, 332 downloads) | highlighted code

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This code i fixed. Can you check for me?

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Re: Interface DHT22 to FPGA

von Lothar M. (lkmiller) (Moderator)

2018-05-21 09:35

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Bùi C. wrote:
> Can you check for me?
Why not checking yourself? And when you find a problem, then we dsicuss 
about that...

But one hint: you are using unsynchronized inputs further on.

        next_bit_in <= singer_bus;
        if  bit_in ='1' and next_bit_in = '0' then  --

next_bit_in is exactly the same async signal like singer_bus. Only 
with a different name. There is no flipflop stage here...

Delete all of the  "next_bit_in <= singer_bus;" assignments and do that 
only once in the "rising_edge(clk)" part:

    elsif rising_edge(clk) then
      state <= next_state; 
      index <= next_index;
      next_bit_in <= singer_bus;
      number_bit <= next_number_bit;
      bit_in     <= next_bit_in;
      data_out   <= next_data_out;
    end if;

This way you have invoked a flipflop for next_bit_in. Only the name of 
this signal is a little bit confusing now...

2018-05-21 17:03: Edited by Moderator

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Re: Interface DHT22 to FPGA

von oswaldo (Guest)

2018-10-02 20:45

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hi, I want to know how to configure the inputs and outputs physically in 
a basys 2, to implement the vhdl code of the dht22 temperature and 
humidity sensor in the planAhead

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