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Forum: FPGA, VHDL & Verilog bits_counter


Author: meido (Guest)
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hello guys hope you are doing well.
so I want to ask you about a simple design to count the number of '1' in 
a serial bus. so when I simulate the counter alone it gives the result 
but when I call it in an other program the  output bits stay at 
"XXXXXXX" so could anyone help me please.
thank you.

Author: Jürgen von der Müllkippe (Guest)
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Sorry my english is not so good, you schaltest two 4017 in line and the 
beiden carry out pins werden OR verknüpft. But one from them must 
invertiert werden. Than you have eine Teilung durch 10.

Author: meido (Guest)
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thank you for your replay
but I didn't understand what you want to say.(it is not a problem if you 
answer using another language)
regards

Author: Lothar M. (lkmiller) (Moderator)
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meido wrote:
> so could anyone help me please
Check out how a test bench is set up in VHDL (the test bench entity has 
no ports!). The strategy is much different to what you do.

How did you generate the clock? By forcing signals? That's the wrong 
way, also...

BTW:  its nearly impossible to edit or cut out source code that's posted 
as a picture. Here are tools to post code as text, so it can be edited 
easily....

: Edited by Moderator
Author: meido (Guest)
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thak ou for your relay
for the clock generation in the global project it is done using the plls 
but the code I posted is just to simplify the task.
also for the test I already did a test bench but I get the same result

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