Verilog task yield "x" for a variable in a timestep

Hi!
In Modelsim SE 10.1a, I tried to code a counter which counts from 0 to 
118 again and again. When the counter reaches #40 and #59, port ctl_1 
and ctl_2 each delivers "1" for 4 period of clocks. Below is my 
code(also attached from files).

But when I simulate, at #40 ctl_1 becomes "x" instead of "1", meanwhile, 
the similar #59 functions just right(wave.jpg shows that). Below is my 
module code. Using tasks is just for the purpose of studying, when I 
give up using task and simply use NBA such as ctl_1 <= 1, the problem 
disappears. Can anyone give any hints? Thanks!