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Forum: FPGA, VHDL & Verilog Verilog task yield "x" for a variable in a timestep


Author: Frank L. (Company: HIT) (frankli998)
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Hi!
In Modelsim SE 10.1a, I tried to code a counter which counts from 0 to 
118 again and again. When the counter reaches #40 and #59, port ctl_1 
and ctl_2 each delivers "1" for 4 period of clocks. Below is my 
code(also attached from files).

But when I simulate, at #40 ctl_1 becomes "x" instead of "1", meanwhile, 
the similar #59 functions just right(wave.jpg shows that). Below is my 
module code. Using tasks is just for the purpose of studying, when I 
give up using task and simply use NBA such as ctl_1 <= 1, the problem 
disappears. Can anyone give any hints? Thanks!

: Edited by User
Author: ElKo (Guest)
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Does it work, if you assign the values directly, without using the 
tasks?

Author: Frank L. (Company: HIT) (frankli998)
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Yes, it does. Without using task, use nonblocking assignment instead, 
everything works fine.

Author: Andy (Guest)
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Have you tried to define the tasks before you us it in the code?
Not sure if it makes any difference, but it looks like the output is 
undefined only on the first call of each task.

Author: Frank L. (Company: HIT) (frankli998)
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The strange thing is that I define ctl_on and ctl_off, #40 does not 
function right but #59 does, I have no idea what's going on...

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