module counter_119 (
  output reg [6:0] dout, reg ctl_1, reg ctl_2,
  input clk, rst);
  parameter ctl_a = 40, ctl_b = 59, delay = 4;
  
  always @ ( posedge clk or posedge rst )  begin
      
      if ((rst) || (dout == 7'b1110110))
        dout <= 7'b0000000;          
      else
        dout <= dout + 0000001;
      
      if ((dout >= ctl_a - 1) && (dout < ctl_a + delay -1)) //minus one here because NBA has not finished LHS update        
        ctl_on(ctl_1);
      else 
        ctl_off(ctl_1);
      
      if ((dout >= ctl_b - 1) && (dout < ctl_b + delay -1)) //minus one here because NBA has not finished LHS update
        ctl_on(ctl_2);
      else 
        ctl_off(ctl_2);
   end
   
   task ctl_on;
    output ctl;
    ctl <= 1;
   endtask
   
   task ctl_off;
    output ctl;
    ctl <= 0;
   endtask
endmodule