EmbDev.net

Forum: FPGA, VHDL & Verilog Width Mismatch in RAM Design


Author: Ed Hower (howerj)
Posted on:

Rate this post
0 useful
not useful
So the issue I am having is that on the line: "data <= 
mem(conv_integer(address));" I get the following error: "width mismatch 
in assignment, target has 8-bits, source has 4-bits."
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram is   
port (
address :in    std_logic_vector ( 3 downto 0); 
data    :inout std_logic_vector ( 7 downto 0); 
cs      :in    std_logic;                                
we      :in    std_logic;                                
oe      :in    std_logic                                 
);
end ram;
architecture beh_ram of ram is
type memory is array (0 to 15)of std_logic_vector (3 downto 0);
signal mem : memory ;
begin
MEM_WRITE:
process (address, data, cs, we) 
begin
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end process;
MEM_READ:
process (address, cs, we, oe, mem) begin
if (cs = '1' and we = '0' and oe = '1')  then               
data <= mem(conv_integer(address));  
else
data <=  (others => 'Z' );
end if;
end process;
end beh_ram;

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Ed H. wrote:
> error: "width mismatch in assignment, target has 8-bits, source has
> 4-bits."
Thats correct.

data is a std_logic_vector ( 7 downto 0), the RAM is a array "of 
std_logic_vector (3 downto 0)".
So, what 4 bits of data do you want to store in the memory?

With this you won't get errors:
mem(conv_integer(address)) <= data(3 downto 0);
data <= "0000" & mem(conv_integer(address));
Wether thats OK to do it that way or not is up to you...

Author: Ed Hower (howerj)
Posted on:

Rate this post
0 useful
not useful
Lothar M. wrote:
> Ed H. wrote:
>> error: "width mismatch in assignment, target has 8-bits, source has
>> 4-bits."
> Thats correct.
>
> data is a std_logic_vector ( 7 downto 0), the RAM is a array "of
> std_logic_vector (3 downto 0)".
> So, what 4 bits of data do you want to store in the memory?
>
> With this you won't get errors:
> mem(conv_integer(address)) <= data(3 downto 0);
> data <= "0000" & mem(conv_integer(address));
> Wether thats OK to do it that way or not is up to you...
So I just changed the array to hold 8-bits as shown below, but now I get 
an error that states "pin data[0]....[7] has multiple drivers."
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram is   
port (
address :in    std_logic_vector ( 3 downto 0); 
data    :inout std_logic_vector ( 7 downto 0); 
cs      :in    std_logic;                                
we      :in    std_logic;                                
oe      :in    std_logic                                 
);
end ram;
architecture beh_ram of ram is
type memory is array (0 to 15)of std_logic_vector (7 downto 0);
signal mem : memory ;
begin
MEM_WRITE:
process (address, data, cs, we) 
begin
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end process;
MEM_READ:
process (address, cs, we, oe, mem) begin
if (cs = '1' and we = '0' and oe = '1')  then               
data <= mem(conv_integer(address));  
else
data <=  (others => 'Z' );
end if;
end process;
end beh_ram;

Author: Markus F. (mfro)
Posted on:

Rate this post
0 useful
not useful
Ed H. wrote:
> "pin data[0]....[7] has multiple drivers."

that might be the case, but not in the code shown as far as I can see.

Author: 42 - Only the right quesions leads to an answer (Guest)
Posted on:

Rate this post
0 useful
not useful
Which Tools throws the error (Simulation, Synthesis)?
Do you really wanout direction inout at the mem?
Does your design holds a correct working Output enable (oe) control?

Do you got a block diagramm showing shared busses?

Author: Ed Hower (howerj)
Posted on:
Attached files:

Rate this post
0 useful
not useful
42 - Only the right quesions leads to an answer wrote:
> Which Tools throws the error (Simulation, Synthesis)?
> Do you really wanout direction inout at the mem?
> Does your design holds a correct working Output enable (oe) control?
>
> Do you got a block diagramm showing shared busses?
Synthesis throws the error.
I will attach my files. I am trying to design a Random Access Memory to 
write 4’b1010 into 16 bit address location of RAM. After complete 
writing, read the data out of the RAM. Also adding clock division to 
this design so that the data can be read out of the RAM at 10 KHz rate 
and display the address and data bus on a logic analyzer.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig