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Forum: FPGA, VHDL & Verilog Verilog code for modulus of negative number query


Author: Lakshita J. (lakshita)
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Hello,

I have written code for calculating modulus of negative number for 
number of bits (n=5),it is giving me correct result for n=5 bits but 
when i increase number of bits for eg n=6,it is giving me incorrect 
result.Why is it so? Should I declare my input or output as signed data 
type to get correct results?
please tell if anybody knows about signed and unsigned data type.

below is my code :-

module negmod #(parameter n = 5) (clk, reset, p, x1,x3,result);
input clk, reset;
input  [n-1:0] p, x1;

output reg  [n-1:0] x3;

output reg result;
wire [n-1:0] y;

assign y =(-x1)+(($floor(-x1/p))* p);
always @(posedge clk) begin
if(reset)begin
x3<=0;
end
else begin
x3<=y;

result<=1;
end
end
endmodule

I have attached 2 simulation results for n=5 and n=6 bits
-3 mod 17= 14 (n=5 )
-3 mod 17 =48 (n=6)

Author: Duke Scarring (Guest)
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Lakshita J. wrote:
> Should I declare my input or output as signed data
> type to get correct results?
Of course. Unsigned data can only represent positive numbers...

Author: Lothar M. (lkmiller) (Moderator)
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Lakshita J. wrote:
> assign y =(-x1)+(($floor(-x1/p))* p);
A hint: split this calculation up into several steps.
Then you can see much more easy where the bug is hidden.

> Should I declare my input or output as signed data type to get correct
> results?
To be honest: I would try that out myself. Before asking in a forum...

: Edited by Moderator
Author: Lakshita J. (lakshita)
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Lothar M. wrote:
> A hint: split this calculation up into several steps.
> Then you can see much more easy where the bug is hidden.

okay.I will try to debug this step-wise. Thanks


> To be honest: I would try that out myself. Before asking in a forum...

I tried it before asking in a forum but I am not getting correct results 
after declaring input as signed type.

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