Verilog code for modulus of negative number query

Hello,

I have written code for calculating modulus of negative number for 
number of bits (n=5),it is giving me correct result for n=5 bits but 
when i increase number of bits for eg n=6,it is giving me incorrect 
result.Why is it so? Should I declare my input or output as signed data 
type to get correct results?
please tell if anybody knows about signed and unsigned data type.

below is my code :-

module negmod #(parameter n = 5) (clk, reset, p, x1,x3,result);
input clk, reset;
input  [n-1:0] p, x1;

output reg  [n-1:0] x3;

output reg result;
wire [n-1:0] y;

assign y =(-x1)+(($floor(-x1/p))* p);
always @(posedge clk) begin
if(reset)begin
x3<=0;
end
else begin
x3<=y;

result<=1;
end
end
endmodule

I have attached 2 simulation results for n=5 and n=6 bits
-3 mod 17= 14 (n=5 )
-3 mod 17 =48 (n=6)