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Forum: FPGA, VHDL & Verilog vivado w/o real board


Author: Elico C. (Company: WS) (elico)
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H all


Is it possible to do a design on VIVDO and simulate it without
 connecting to it a real physical board just using some text file
 that wil accept that design and enable simulating it ?

Thanks
Elico

Author: Yesman (Guest)
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Yes, you can.

Author: Lothar M. (lkmiller) (Moderator)
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Elico C. wrote:
> Is it possible to do a design on VIVDO and simulate it without
>  connecting to it a real physical board just using some text file
Not only that it's possible, that's the usual way:
write a hardware description and write a testbench and then simulate the 
first with (or better against) the second.

: Edited by Moderator
Author: Elico C. (Company: WS) (elico)
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Thanks
Elico

Author: Elico C. (Company: WS) (elico)
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Hi

Is it possible to do with VIVADO virtual synthesis of some design
 without connecting a real board,
 just by saving the design to some text file and indicating the name of 
the virtual board so that we will see the "would be " results that we 
will
receive with that kind of board and "would be " FPGA chip in case we 
will use such real board ?

Thanks
Elico

Author: Lothar M. (lkmiller) (Moderator)
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Elico C. wrote:
> and indicating the name of the virtual board
What "virtual board"?
You do not need any kind of board to synthesize a design...

I urge you to get clear about the processing steps in the FPGA design 
toolchain! When you don't know your toolchain then you don't know what 
tool to use for what job. Finally you end by using a hammer to drive in 
a screw.

To check out the size of design simply synthesize it not for a specific 
FPGA, but for a complete family.

Or select the biggest FPGA in a family and synthesize the design for 
that. Then you can see the resource needs of that design.

: Edited by Moderator
Author: Elico C. (Company: WS) (elico)
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Thanks

Elico

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