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Forum: FPGA, VHDL & Verilog library ieee; use ieee.std_logic_1164.all;


Author: Elico C. (Company: WS) (elico)
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The "use std _logic_1164.all"

When I write a VHDL design how do I know what ieee libraries to use in 
the design ?

Thanks
Elico

Author: bitwurschtler (Guest)
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Eliahu C. wrote:
> When I write a VHDL design how do I know what ieee libraries to use in
> the design ?

B'coze you're intending to use one of the functions etc. declared in 
this lib and your synthesis tool is supporting it.

http://soc.eurecom.fr/EDC/lectures/vhdl/1164pkg.pdf

Author: Lothar M. (lkmiller) (Moderator)
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Eliahu C. wrote:
> When I write a VHDL design how do I know what ieee libraries to use in
> the design ?
In fact you do not need any libraries. But when you don't invoke some 
of them, then you must write all the type definitions and all the data 
conversion and data handling functions on your own. To keep that 
effort low you use those packages you need.

So its simple: in your design you use those libraries you need.

When you want to convert an integer to a vector, then you either 
invoike the old fashioned std_logic_arith packages or the numeric_std 
package. But it is no good solution to think: "I invoke all of all 
possible packages I can find!", because then you will encounter curious 
errors and strange behavior now and then...

So its simple: in your design you use those libraries you need. And 
no more else!

: Edited by Moderator

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