Illegal output or inout port connection for port 'Aout'

Michael Guest 2018-02-24 21:06 #5328411

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I have been trying to get this to work for quite sometime and I dont 
know why I cant simulate. It says error with port 'Aout'. Below is each 
of my modules that I have created. Please let me know. Thank you very 
much

// ALU TestBench
`timescale 1ns/1ps
module ALU_tb();
reg [3:0] A, B, OPCODE;
wire [3:0] ALU_out;
wire Cout, OF;
ALU A1 (A, B, Cin, OPCODE, ALU_out, Cout, OF);
initial begin
//OPCODE 0000 and 0001, A=0101, B=0010;
A = 4'b0101; B = 4'b0010; Cin = 'b0; OPCODE = 4'b0000; #5;
$display("OPCODE = %b, A = %b, B = %b, ALU_out = %b, Cout = %b, OF = %b", OPCODE, A, B, ALU_out, Cout, OF);
OPCODE = 4'b0001; #5;
$display("OPCODE = %b, A = %b, B = %b, ALU_out = %b, Cout = %b, OF = %b", OPCODE, A, B, ALU_out, Cout, OF);
//OPCODE 0000, 0001, and 0010, A=0011, B=0001;
A = 4'b0011; B = 4'b0001; Cin = 'b0; OPCODE = 4'b0000; #5;
$display("OPCODE = %b, A = %b, B = %b, ALU_out = %b, Cout = %b, OF = %b", OPCODE, A, B, ALU_out, Cout, OF);
OPCODE = 4'b0001; #5;
$display("OPCODE = %b, A = %b, B = %b, ALU_out = %b, Cout = %b, OF = %b", OPCODE, A, B, ALU_out, Cout, OF);
OPCODE = 4'b0010; #5;
$display("OPCODE = %b, A = %b, B = %b, ALU_out = %b, Cout = %b, OF = %b", OPCODE, A, B, ALU_out, Cout, OF);
//OPCODE 0000 and 0001, A=0100, B=0011;
A = 4'b0100; B = 4'b0011; Cin = 'b0; OPCODE = 4'b0000; #5;
$display("OPCODE = %b, A = %b, B = %b, ALU_out = %b, Cout = %b, OF = %b", OPCODE, A, B, ALU_out, Cout, OF);
OPCODE = 4'b0001; #5;
$display("OPCODE = %b, A = %b, B = %b, ALU_out = %b, Cout = %b, OF = %b", OPCODE, A, B, ALU_out, Cout, OF);
endmodule
module ALU(input [3:0] A, B, input Cin, input [3:0] OPCODE, output [3:0] ALU_out, output Cout, OF);
reg [3:0] Ain, Bin, Bn;
wire [3:0] Sum;
wire CoutFA, OFFA;
reg [3:0] ALU_out_;
reg Cout_, OF_;
comp2s C1 (B,Bn);
fulladder4 FA4 (Ain, Bin, Cin, Sum, CoutFA, OFFA);
assign ALU_out = ALU_out_;
assign Cout = Cout_;
assign OF = OF_;
always @ (*) begin
Ain = 4'b0000; Bin = 4'b0000; ALU_out_ = 4'b0000; Cout_ = 1'b0; OF_ = 1'b0;
case(OPCODE)
4'b0000 : begin
Ain = A;
Bin = B;
ALU_out_ = Sum;
Cout_ = CoutFA;
OF_ = OFFA;
4'b0001 : begin
Ain = A;
Bin = Bn;
ALU_out_ = Sum;
Cout_ = CoutFA;
OF_ = OFFA;
4'b0010 : begin
ALU_out_ = A&B;
Cout_ = 4'd0;
OF_ = 4'd0;
default : begin Ain = 4'b0000; Bin = 4'b0000; ALU_out_ = 4'b0000; Cout_ = 1'b0; OF_ = 1'b0;
endmodule
// 2's compliment
module comp2s(input [3:0] A, output [3:0] Aout);
wire Cout, OF;
wire [3:0] An;
assign An=~A;
fulladder4 FA4 (An, 4'd0, 1'b1, Aout, Cout, OF);
endmodule
// ripple adder
module fulladder4(input [3:0] A, B, input Cin, output [3:0] Sum, output Cout, OF);
wire Cout1, Cout2, Cout3;
fulladder FA1 (A[0], B[0], Cin, Sum[0], Cout1);
fulladder FA2 (A[1], B[1], Cout1, Sum[1], Cout2);
fulladder FA3 (A[2], B[2], Cout2, Sum[2], Cout3);
fulladder FA4 (A[3], B[3], Cout3, Sum[3], Cout);
xor X1 (OF, Cout3, Cout);
endmodule
//Full adder
module fulladder(input A, B, Cin, output Sum, Cout);
halfadder HA1 (A,B,Sum1, Cout1);
halfadder HA2 (Sum1,Cin,Sum,Cout2);
or O1 (Cout, Cout1, Cout2);
endmodule
//half adder
module halfadder(input A, B, output Sum, Cout);
assign Sum=A^B;
assign Cout=A&B;
endmodule

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