Hello, from the theory in the attached photo i have implemented the formula in the VERILOG code bellow, the syntax check was fine but when i tried in XILINX to force values the simulation gives me an empty screen and says: # run 1.00us INFO: Simulator is stopped. where did i go wrong in entering the coefficients? Thanks
module vvco(fo,vctl,kv); input fo,vctl,kv; reg vco_b=1'b0; reg fo_b=3'b0; reg vctl_b=3'b0; reg kv_b=3'b0; always #((1/fo_b-vctl_b*kv_b/fo_b^2)/2) vco_b<=~vco_b; endmodule
: Edited by User
Rock B. wrote: > i tried in XILINX to force values I never worked with forced values to simulate a design. I usually write testbench to check my code and apply different stimuli. Duke
I am also facing the same problem.
maybe it is not supported by your simulator, as noted in the last paragraph of your document