`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: CPP // Engineer: Fadi // Create Date: 01/25/2018 11:07:19 PM // Design Name: // Module Name: regfile // Project Name: // Revision: // Revision 0.01 - File Created // Additional Comments: ////////////////////////////////////////////////////////////////////////////////// /* module alu(input [31:0] a,b, input [2:0] alucont, output reg [31:0] result, output zero); wire [31:0] b2 , sum, slt; */ module alu(input logic [31:0] a,b, input logic [2:0] opcode, output logic [31:0] aluout, output logic zero); logic [31:0] b2 , sum, slt; assign b2 = opcode[2] ? ~b:b; assign sum = a + b2 + opcode[2]; //addition assign slt= sum[31]; // Set less than always @ (*) begin case (opcode[1:0]) 2'b00: aluout <= a & b2; // A & B OR 2'b01: aluout <= a | b2; //A | B AND 2'b10: aluout <= sum; // A+B , A-B 2'b11: aluout <= slt; endcase end assign zero = (aluout == 32'b0); endmodule