Testbench for count zero combinational

Verilog Testbench

Count Zeros wrote:
> Please help me making tesbench about this?
Helping means: you start something, you encounter a specific problem, 
then you post what you have and then someone may help you fixing that 
problem.

It does not mean: doing your homework.

A testbench is fairly easy here:
Do this in an (endless) loop:
1. generate a random binary number
2. calculate the count of zeros in that number in your way
3. pass the random number to the count_zeros module
4. compare your result with that from the count_zeros module
5. halt the simulation and raise an error if count_zero reports an error
6. halt the simulation and raise an error if the results are different
7. goto 1.

 Thats all.

Sorry sir

Is this correct?

module countzeros_tb();
  reg [7:0] in;
  reg [7:0] x;
  wire [3:0] out;


Or i will remove the x? Im not familiar with the function legal.
and i can't find related topic about count zeros.

Dennis B. wrote:
> Im not familiar with the function legal.
It looks much alike you must write this function (which obviously checks 
the input value for validity) on your own.

> and i can't find related topic about count zeros.
Use that grey thing between your ears...

Given a (binary) input vector of 10101010 tell me:
how many 0 (= zeros) do you see in it?

If your answer is 4, then: congratulation, you know how to count zeros!
Now you simply must write that way of calculation down in Verilog.