EmbDev.net

Forum: FPGA, VHDL & Verilog Testbench for count zero combinational


Author: Count Zeros (Guest)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Please help me making tesbench about this? I badly needed Thanks :)

Author: Dennis Bacarisas (Company: none) (ohyaah123)
Posted on:

Rate this post
0 useful
not useful
Verilog Testbench

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Count Zeros wrote:
> Please help me making tesbench about this?
Helping means: you start something, you encounter a specific problem, 
then you post what you have and then someone may help you fixing that 
problem.

It does not mean: doing your homework.

A testbench is fairly easy here:
Do this in an (endless) loop:
1. generate a random binary number
2. calculate the count of zeros in that number in your way
3. pass the random number to the count_zeros module
4. compare your result with that from the count_zeros module
5. halt the simulation and raise an error if count_zero reports an error
6. halt the simulation and raise an error if the results are different
7. goto 1.

 Thats all.

: Edited by Moderator
Author: Dennis Bacarisas (Company: none) (ohyaah123)
Posted on:

Rate this post
0 useful
not useful
Sorry sir

Is this correct?

module countzeros_tb();
  reg [7:0] in;
  reg [7:0] x;
  wire [3:0] out;


Or i will remove the x? Im not familiar with the function legal.
and i can't find related topic about count zeros.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Dennis B. wrote:
> Im not familiar with the function legal.
It looks much alike you must write this function (which obviously checks 
the input value for validity) on your own.

> and i can't find related topic about count zeros.
Use that grey thing between your ears...

Given a (binary) input vector of 10101010 tell me:
how many 0 (= zeros) do you see in it?

If your answer is 4, then: congratulation, you know how to count zeros!
Now you simply must write that way of calculation down in Verilog.

: Edited by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig