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Forum: FPGA, VHDL & Verilog Simulation delay unexpected & Stx value


Author: Blas Molina (b_aprentice)
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Hi,
I have done a TB in Verilog with a selfcheck loop and I have 2 registers 
where I compare the expected and actual output value:
reg [MODULES:0] count_comp(expected), count(actual value);

Because the output from the UUT is registered, I am expecting 1 Clock 
PERIOD  delay but from the simulation I got 2 PERIODS and Undefined 
signal. The module is testing a "unsigned" adder with 4 bits

Any idea why I get the StX values after the Enable signal goes High?
And why there are 2 clock periods delay between the expected and actual 
signal?

TB self-check coding below

always begin
    for ( i=0; i < LOOP; i = i + 1 ) begin
          for (b=0; b < LOOP; b = b + 1) begin
                            in1 = i;
          in2 = b;
          count_comp = in1 + in2;
          #PERIOD;
          count = {carry, sum};
                if (count != count_comp) begin
                    $display ("Error at time %d", $time);
                    $display ("Expected value: %d, Value calculated: 
%d", count_comp, count);

Author: Klakx (Guest)
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I suggest you give us a better piece of code, even verilog requires at 
least a 'end' for 'if'/'for'/'begin'

Author: ElKo (Guest)
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Remove the clock from your adder.

Try to gather the result a split second earlier. Otherwise it is somehow 
random, which block is executed first.
          count_comp = in1 + in2;
          #PERIOD-1;
          count = {carry, sum};
                if (count != count_comp) begin
                    $display ("Error at time %d", $time);
                    $display ("Expected value: %d, Value calculated: 
%d", count_comp, count);
          #1;

Show your full code, including the adder!

Author: Blas Molina (b_aprentice)
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Sorry for having posted a sort piece of code before, I am a newbie with 
Forums and posting.
Bellow is my full testbench in Verilog
The Adder is an unsigned adder in VHDL.
looking at the code, I would believe the only time the output values are 
registered (s and cy_out) is at the "Funct_NbitsAdder" module. So that, 
I was expecting to see 1 PERIOD delay between the calculated and the 
actual output value.
In fact , the value "sum" from the TB which it is defined as a wire, has 
the expected delay of a PERIOD ( this is the actual output from the 
"Funct_NbitsAdder". When that value is concatenated in the reg "comp" 
signal, the value has 2 PERIOD delay.
Is this due to the fact that reg definition works as a register and 
updates the values at the next clokc period?
If so, I have also tried to define "reg [MODULES:0] count_comp, count;" 
as a wires -> "wire [MODULES:0] count_comp, count;" but the tool gave me 
an error during compilation.
module tb_SignAdder();

parameter PERIOD = 10; // 10 ns -> 100MHz
parameter MODULES = 4;  // N number of adders/bits
parameter LOOP = 2**MODULES; // Max loop iterations 


reg [MODULES-1:0] in1;
reg [MODULES-1:0] in2;
reg cy_in;
reg clk;
reg en,rst;
wire [MODULES-1:0] sum;
wire carry;
integer i,b;
reg [MODULES:0] count_comp, count;




//Specify the VHDL architecture with the whole definition : <lib>.<module>.<architecture>
\xil_defaultlib.Funct_NbitsAdder(num_usigned) #(MODULES) uut ( 
                    .a(in1),
                    .b(in2),
                    .cy_in(cy_in),
                    .clk(clk),
                    .en(en),
                    .rst(rst),
                    .s(sum),
                    .cy_out(carry) );

// Init & Test En
initial begin 
$display("----------------------\n %d Bit Full-Adder\n----------------------\n", MODULES);
// Initialization of stimulus
in1 = 0; in2 = 0; cy_in = 0; clk= 1; en = 0; rst = 1;
#PERIOD rst = 0;
#(PERIOD*3) en = 1;
end

// Clock signal generation
always 
  #(PERIOD/2) clk = ~clk;

//Asyn process with input stimulus
always begin
    for ( i=0; i < LOOP; i = i + 1 ) begin
          for (b=0; b < LOOP; b = b + 1) begin
                in1 = i;
          in2 = b;
          count_comp = in1 + in2;
          #PERIOD;
          count = {carry, sum};
                if (count != count_comp) begin
                    $display ("Error at time %d", $time);
                    $display ("Expected value: %d, Value calculated: %d", count_comp, count);
                end
              end
    end
end
endmodule

With the Adder being represented by a unsigned module in VHDL
entity Funct_NbitsAdder is
generic (  numbits : integer := 2);
           
    Port ( a : in STD_LOGIC_VECTOR (numbits-1 downto 0):= (others=>'0');
           b : in std_logic_vector (numbits-1 downto 0):= (others=>'0');
           cy_in : in std_logic:='0';
         clk : in std_logic:='0';
         en : in std_logic:='0';
         rst : in std_logic:='0';
           s : out std_logic_vector (numbits-1 downto 0);
           cy_out : out std_logic);
end Funct_NbitsAdder;

-------------------------------
--- Unsigned addition!! -------
------------------------------- 
architecture num_usigned of Funct_NbitsAdder is
signal sum : unsigned (numbits downto 0):= (others=>'0');  
signal carry_out : unsigned (numbits downto 0):= (others=>'0');
constant zero : unsigned (numbits-1 downto 0):= (others =>'0');

begin
--Synchronous Reset and Enable
reg_outputs: process (clk)
begin
  if (clk'event and clk='1') then
      if (rst='1') then 
         s<=(others =>'0');
         cy_out <= '0';
      elsif (en='1') then
         carry_out <= zero & cy_in;
         sum <= ('0' & unsigned(a)) + ('0' & unsigned(b))+ carry_out;
          s <= std_logic_vector(sum(numbits-1 downto 0));
          cy_out <= sum(numbits);
      else
        s <= (others =>'0');
        cy_out <= '0';         
      end if;
  end if;
end process;
end num_usigned;

Author: Lothar Miller (lkmiller) (Moderator)
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Blas M. wrote:
> --- Unsigned addition!! -------
An addition is a completely combinatorial job. Why do you invoke a clock 
there?

Author: ElKo (Guest)
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Lothar M. wrote:
> An addition is a completely combinatorial job. Why do you invoke a clock
> there?
I agree.

Blas M. wrote:
> Is this due to the fact that reg definition works as a register and
> updates the values at the next clokc period?
No, it is not the definition as reg. It is the description of a clocked 
(registered) process in the adder: "if (clk'event and clk='1') then"

The second clock cycle might be a race condition. After #PERIOD the 
signals in1, in2 and clk are changing. But in which order? If clk 
changes first, the adder is executed with the old values. After that the 
new values are applied to the adder and the next wait-Period follows.
Change the testbench, that clk and the singlas are not changing in the 
same moment!

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