SISO Shift Register

von Dayana (Guest)

2017-12-01 14:58

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Hello everyone.

Current Im designing 3x8 shift right SISO

Below is my verilog code:

`timescale 1ns / 1ps
module ShiftReg (Clk,En,In,Out);
parameter InWidth = 3;
parameter Length = 8;
input Clk,En;
input  [InWidth-1:0] In;
output [InWidth-1:0] Out;
reg [Length-1:0] sr ;
always@(posedge Clk)
  if (En == 1'b1)
    sr[0] <= In;
    sr <= sr<<1;
assign Out = sr[Length-1];
endmodule


However this is my warning:

WARNING:HDLCompiler:413 - 
"C:\Users\User\Desktop\PE\ShiftReg\ShiftReg\ShiftReg.v" Line 17: Result 
of 3-bit expression is truncated to fit in 1-bit target.
WARNING:Xst:647 - Input <In> is never used. This port will be preserved 
and left unconnected if it belongs to a top-level block or it belongs to 
a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1710 - FF/Latch <sr_0> (without init value) has a constant 
value of 0 in block <ShiftReg>. This FF/Latch will be trimmed during the 
optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_1> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_2> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_3> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_4> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_5> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_6> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_7> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <sr_0> (without init value) has a constant 
value of 0 in block <ShiftReg>. This FF/Latch will be trimmed during the 
optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_1> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_2> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_3> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_4> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_5> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_6> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_7> 
(without init value) has a constant value of 0 in block <ShiftReg>. This 
FF/Latch will be trimmed during the optimization process.

Does anyone have any idea for my input problem?

Thank you very much

2017-12-01 15:34: Edited by Moderator

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Re: SISO Shift Register

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-12-01 15:45

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Dayana wrote:
> However this is my warning:
> WARNING:HDLCompiler:413 -
> "C:\Users\User\Desktop\PE\ShiftReg\ShiftReg\ShiftReg.v" Line 17: Result
> of 3-bit expression is truncated to fit in 1-bit target.
A hint: try to write your code without those generics/constants, but 
with numbers in each signal and register definition. Then you will see, 
that the line "sr[0] <= In;" is trying to pack a input vector "In" of 
three bits width in a single flipflop "sr[0]".

What do you want to get with that code?
Should sr be a shift register to delay those In vectors?

Then you may have a look for "multidimensional arrays in Verilog":
https://www.google.com/search?q=multidimensional+arrays+in+verilog
https://stackoverflow.com/questions/3011510/how-to-declare-and-use-1d-and-2d-byte-arrays-in-verilog

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Re: SISO Shift Register

von Dayana S. (dayanasaiful)

2017-12-01 16:39

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Emmm I dont really understand the hint ...  Sorry for my lack of 
knowledge.

Actually I want to preload my 3 bit data into my systolic array.

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Re: SISO Shift Register

von Tim (Guest)

2017-12-01 17:07

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does it work in Simulation?

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Re: SISO Shift Register

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-12-01 17:42

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Dayana S. wrote:
> Actually I want to preload my 3 bit data into my systolic array.
Do you want to store 3 bits in parallel (in 3 of those 8 bit shift 
registers) or should they be stored one after the other in 1 shift 
register? If the second: how do 8 bits length match with 3 input bits?

> Emmm I dont really understand the hint ...
Draw a structure of your shift register on a sheet of paper. Then we 
have something to discuss about...

Tim wrote:
> does it work in Simulation?
For sure not. You simply can't assign a input vector of 3 bits width to 
a shift register with 1 bit width...

2017-12-01 17:45: Edited by Moderator

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Re: SISO Shift Register

von Dayana S. (dayanasaiful)

2017-12-02 01:20

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No. Its a 3X8 Shift In Shift Out Register

The output of the SISO will be connected to  Sytolic array Input.

True it doesnt work

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Re: SISO Shift Register

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-12-02 08:42

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Dayana S. wrote:
> Its a 3X8 Shift In Shift Out Register
At the moment you have a 1x8 Shift Register. As I said: you have to add 
one dimension...

I don't do Verilog, but it should be something like that:

reg [Length-1:0][InWidth-1:0] sr;

At the end it should give an array of 24 flipflops arranged in some way 
like 8x3...

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Re: SISO Shift Register

von Dayana S. (dayanasaiful)

2017-12-02 10:10

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> At the moment you have a 1x8 Shift Register. As I said: you have to add
> one dimension...

Dimension?

> I don't do Verilog, but it should be something like that:reg
> [Length-1:0][InWidth-1:0] sr;
> At the end it should give an array of 24 flipflops arranged in some way
> like 8x3...

Ive tried this but verilog doesnt used this type of operation? Maybe any 
other idea?

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Re: SISO Shift Register

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-12-02 13:20

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Dayana S. wrote:
> Maybe any other idea?
According to the link I posted earlier in this thread I would try it 
this way:
reg [InWidth-1:0] sr [Length-1:0];

And if it's not working it would turn around the range:
reg [InWidth-1:0] sr [0:Length-1];

And if that doesn't do the job and if I were a student I would go to my 
university's library  and have a look for any Verilog book. It's in 
there for sure...

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Re: SISO Shift Register

von Andi (Guest)

2017-12-02 14:39

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Instead of a 2 dimensional array, you can also use a 24bit register and 
shift by 3:

`timescale 1ns / 1ps
module ShiftReg (Clk,En,In,Out);
input Clk,En;
input  [2:0] In;
output [2:0] Out;
reg [23:0] sr ;            //3 x 8 bits = 24
always@(posedge Clk)
  if (En == 1'b1)
    sr <= {sr[20:0],In};   //shift by 3 and concatenate Input
assign Out = sr[23:21];    //top 3 bits to output
endmodule

I've done it with literal numbers instead of parameters, so it's more 
readable.

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Re: SISO Shift Register

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-12-02 14:51

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Andi wrote:
> Instead of a 2 dimensional array, you can also use a 24bit register and
> shift by 3
And of course you can drive in a screw with a sledgehammer...

The one that doesn't like or doesn't understand 2-dimensional arrays, 
that one may try it with 3 explicit shift registers like this:

timescale 1ns / 1ps
module ShiftReg (Clk,En,In,Out);
input Clk,En;
input  [2:0] In;
output [2:0] Out;
reg [7:0] sr0;
reg [7:0] sr1;
reg [7:0] sr2;
always@(posedge Clk)
  if (En == 1'b1)
    sr0 <= In[0];
    sr1 <= In[1];
    sr2 <= In[2];
assign Out[0]= sr0[7];
assign Out[1]= sr1[7];
assign Out[2]= sr2[7];
endmodule

2017-12-02 15:16: Edited by Moderator

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Re: SISO Shift Register

von Dayana S. (dayanasaiful)

2017-12-02 16:00

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Andi

Thank you very much. It works well.

and

thanks also to others that gave ideas and suggestions.

I really appreciate it.

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Re: SISO Shift Register

von Andi (Guest)

2017-12-02 16:53

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Lothar M. wrote:
> And of course you can drive in a screw with a sledgehammer...

Screws, hammers, nails or screwdrivers, at the end all is broken down to 
LUTs and FlipFlops ;-)

The Verilog compiler will produce the same output, if you shift by 3, 
shift 3 times by 1 or move an element of a 3bit two dimensinal array, so 
why not take the one that is easiest to write.

Andi

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Re: SISO Shift Register

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-12-02 23:31

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Andi wrote:
> Lothar M. wrote:
>> And of course you can drive in a screw with a sledgehammer...
> Screws, hammers, nails or screwdrivers, at the end all is broken down to
> LUTs and FlipFlops ;-)
You are right, but Dayana now learned a workaround  by hammering the 
screw straightaway into the wall instead of selecting the correct tool 
for the task.
And keep in mind: for one only knowing a hammer the whole world looks 
like a nail.  ;-)

> The Verilog compiler will produce the same output, if you shift by 3,
> shift 3 times by 1 or move an element of a 3bit two dimensinal array, so
> why not take the one that is easiest to write.
The "easiest" would be learning a bit about arrays and using them in the 
future as the correct tool:

`timescale 1ns / 1ps
module ShiftReg (Clk,En,In,Out);
parameter InWidth = 3;
parameter Length = 8;
input Clk,En;
input  [InWidth-1:0] In;
output [InWidth-1:0] Out;
reg [InWidth-1:0] sr [Length-1:0];
integer i;
always@(posedge Clk)
  if (En == 1'b1)
    for (i=1; i<Length; i=i+1) sr[i] <= sr[i-1];
    sr[0] <= In;
assign Out = sr[Length-1];
endmodule

The whole thing can be found at 
http://www.bitweenie.com/listings/verilog-shift-register/

2017-12-03 09:35: Edited by Moderator

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