If i have two entity's:i.e entity 1 port( send:out standard_logic; ); end architecture (function carried out) send<=signal end entity 2 port( receive:in standard_logic; ); end architecture (function carried out) end this code is a basic concept of the task i am trying to carry out. I have tried to link send in entity 1 with receive in entity 2,i have tried port map but i hasn't worked. are signals a better way of connecting the two entity together. input receive (in entity 2) <= signal send in entity 1. does this need port map in each body of the architecture.
Richard T. wrote: > but i hasn't worked. What didn't work with what error message? Read the chapter "component instantiation" and afterwards the chapter "port map" in any VHDL book. Having done that you will see tere are 2 ways: a. instantiate entity 2 as a component in entity 1and simply assign the port signals b. wirte a third entity, instantiate both of the entities 1 and 2 as components and wire them together using a local signal. The second way is the most probable way in your case.. As already said a few times ago (eg in https://embdev.net/topic/440226?goto=5227182#5227123 ): pls use the [vhdl] tags to wrap your code...
I have managed to get it to connect now,i did not realize you have to include all of the ports in the entity, i thought that inside the brackets()would indicate the specific port only. connection:entity work.entity(entity_architecture) port(transmission,in1) it forced me to include reset,clock etc.