Richard T. wrote:
> Type  dataflow is array ( 0 to 6) of std_logic_vector (6 downto 0);
> signal data1: dataflow :=(12,0,6,5-6,-7,-78)
How can this work? data1 contains 7 std_logic_vectors, you cannot assign 
integer numbers to them...

> i have tried lots of ways making the logic vector an integer array but
> cant seem to find a way of either storing it in this way or adding the
> values once converted to a positive or negative integer.
What do you want at all?

BTW: pls use the [vhdl] tags wrapped around your VHDL code like 
described in the "formatting options" a few lines above every edit box.

srry some of my explanation was missing
(12,0,6,5,-6,-7,-78)

i would like to send this type of information to an output and thought i 
would need to put it into an array 7 long.

i have little programming experience in vhdl

each time a clock cycle happens i want the next integer to be sent, is 
it better to use case statements to do this or can i create an array 
with seven values inside that release another integer on a clock cycle.

thnx

Richard T. wrote:
> or can i create an array with seven values inside that release another
> integer on a clock cycle.
VHDL has a very strict type handling.
You cannot simply assign an integer to a std_logic_vector!

One thing in advance: -78 does not fit in 7 bits!

Having cleared that I would do it this way:

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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:

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:

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type dataflow is array (0 to 6) of integer range -128 to 127;

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signal data  : dataflow := (12,0,6,5-6,-7,-61);

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signal index : integer range 0 to 6 := 0;

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:

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:

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  dataflow <= std_logic_vector(signed(data(index),7));

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:

i will play with this,i set the 7 bits thinking i was partitioning 7 
bits of data but i see your using the space to generate the integer.

i used very similar code hours ago but i had range at 0 to 7 and i 
didn't have the signal index. i guess this is a sub type of the array 
showing length?

thank you for helping i been working on this for days and couldn't find 
any similar examples to try and understand the manipulation of the code.

this expression is contained within the architecture.

type dataflow is array (0 to 6) of integer range -128 to 127;
signal data  : dataflow := (12,0,6,5-6,-7,-61);
signal index : integer range 0 to 6 := 0;

where in the body of the program does this fit?
dataflow <= std_logic_vector(signed(data(index),7));

this indicates the makeup of the array but if i want to connect it to an 
output, output_1<=data wont suffice will it. does the output have to be 
of a certain type e.g integer or std_logic_vector(7 downto 0)

Richard T. wrote:
> the signal index. i guess this is a sub type of the array showing length?
It is what you wanted, when you increment the index every clock cycle:
Richard T. wrote:
> an array with seven values inside that release another integer on a
> clock cycle.

So, lets finish it up:

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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entity PatternGenerator is

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    Port ( clk : in  STD_LOGIC;

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           pattern : out  STD_LOGIC_VECTOR (6 downto 0));

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end PatternGenerator;

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architecture Behavioral of PatternGenerator is

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  type dataflow is array (0 to 6) of integer range -64 to 63;

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  signal data  : dataflow := (12,0,6,5,-6,-7,-38);

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  signal index : integer range 0 to 6 := 0;

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begin

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  process begin

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     wait until rising_edge(clk);

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     if index<6 then  index <= index+1;

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     else             index <= 0;

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     end if;

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  end process;

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  pattern <= std_logic_vector(to_signed(data(index),7));

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end Behavioral;

After applying a clock it looks as expected...

thank you very much all working well and now can understand process.