Ok, so I need some help with a verilog self learning project I'm working on. I'm building a 16 bit RISC microprocessor. I'm on the last 3 modules before major testing and I'm stuck on the second one. The instruction decoder. I'll have a diagram to explain what I'm talking about. The module takes a 16 bit input First 4 bits raise a flag that corresponds to the instruction (ex. MOV, ADD, ADDI, SUB, NOT, AND, OR, etc.) the last 12 bits break down into 6 and 6 for holders to do the operation. I've also attached my code to what I think is correct. Does this look ok? Is this how you would implement this? Did I over complicate it.
MikeERSan wrote: > Did I over complicate it. I'm not the Verilog pro, but as far as I see, you kind of assign the op to itself... Why the doublestep with assigning op codes to the op codes? I would do it somehow this way without the if-query:
always @* begin
op = instruction[15:12];
param1 = instruction[11:6];
param2 = instruction[5:0];
always @(posedge clk)
4'b0010: //pick the FSM that does MOV with param1 & param2
4'b0011: //pick the FSM that does ADD with param1 & param2
4'b0100: //pick the FSM that does ADDi with param1 & param2
4'b1101: //pick the FSM that does LOAD with param1 & param2
4'b1110: //pick the FSM that does STORE with param1 & param2
BTW: this is not a 16-Bit processor, because its operands are obviously only 6 bits wide. Therefore I would call it a 6 bit processor. Otherwise the AVR family also would be a 16 bit processor, because the command word width within them is 16 bits...
: Edited by Moderator
Here you will find an example code of a very small and simple CPU. https://embeddedmicro.com/tutorials/lucid/basic-cpu It is very fast, simple, and it is running fine. Hope you will find an inspiration for your project. This is written in Lucid. But Lucid will be compiled into Verilog. Download the free Mojo IDE and compile this example. You will find the Verilog code in a sub directory.
imho a 16bit processor is defined by the databus (and thus a 16bit ALU) and not by the width of the opcode. Therefore, it is a 16bit CPU.
Tim wrote: > Therefore, it is a 16bit CPU. Probably. But a pretty crippled one considering you need three instructions to load a 16-bit value anywhere...