Verilog 16 bit RISC Microprocessor

MikeERSan wrote:
> Did I over complicate it.
I'm not the Verilog pro, but as far as I see, you kind of assign the op 
to itself...

Why the doublestep with assigning op codes to the op codes? I would do 
it somehow this way without the if-query:

1

  always @* begin

2

    op = instruction[15:12];

3

    param1 = instruction[11:6];

4

    param2 = instruction[5:0];

5

  end  

6

  always @(posedge clk)

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    case (op)

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      4'b0010: //pick the FSM that does MOV with param1 & param2

9

      4'b0011: //pick the FSM that does ADD with param1 & param2

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      4'b0100: //pick the FSM that does ADDi with param1 & param2

11

      :

12

      :

13

      4'b1101: //pick the FSM that does LOAD with param1 & param2

14

      4'b1110: //pick the FSM that does STORE with param1 & param2

15

    endcase

BTW: this is not a 16-Bit processor, because its operands are 
obviously only 6 bits wide. Therefore I would call it a 6 bit processor. 
Otherwise the AVR family also would be a 16 bit processor, because the 
command word width within them is 16 bits...

Here you will find an example code of a very small and simple CPU.

https://embeddedmicro.com/tutorials/lucid/basic-cpu

It is very fast, simple, and it is running fine.
Hope you will find an inspiration for your project.


This is written in Lucid.
But Lucid will be compiled into Verilog.
Download the free Mojo IDE and compile this example.
You will find the Verilog code in a sub directory.

Tim wrote:
> Therefore, it is a 16bit CPU.

Probably.

But a pretty crippled one considering you need three instructions to 
load a 16-bit value anywhere...