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Forum: FPGA, VHDL & Verilog Integer Assignment to STD_LOGIC_VECTOR


Author: Rejoy Mathews (Company: Lab Instructor) (rejoymathews32)
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For a 3-8 Decoder my IO ports are as below:

d : in STD_LOGIC_VECTOR (2 downto 0);
o : out STD_LOGIC_VECTOR (7 downto 0));

In my VHDL code, I am trying to mimic a Verilog assignment where d is 
used in the case statement as the case parameter and o is the output.

Verilog syntax is as below:
3’d7: o=8’d1;

In my VHDL case statement I could come up with the below assignment
case d is
when "111" => o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8));

Is there an easier way of doing the same without using Type conversions 
in VHDL. Something like the code below (Although this will return a 
compile error).

case d is
when 7 => o <= 1;

Thanks in advance.


Also, could someone explain how the type conversions is working using 
the below syntax.

o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8));

Author: Dussel (Guest)
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Rejoy M. wrote:
> In my VHDL case statement I could come up with the below assignment
> case d is
> when "111" => o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8));
>
> Is there an easier way of doing the same without using Type conversions
> in VHDL.
There are literals in VHDL. It's either like x"1" or 16#1#. You can try 
one of those or search for "literals".

Rejoy M. wrote:
> Also, could someone explain how the type conversions is working using
> the below syntax.
>
> o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8));
What do you want to know? Why it has to be this way?
Unsigned is just another interpretation of a std_logic_vector. A 
std_logic_vector is a string of independent bits, whereas unsigned is a 
positive (or zero) number represented by those bits. That's why you can 
simply cast between unsigned and std_logic_vector.
An integer is a number, which has nothing to do with VHDL bits. So you 
have to convert the integer into a bit representation via a conversion 
function. That's why you have to give the length as parameter. The 
integer 1 could be represented as binary "1", "01", "001", so the 
compiler has to know, how long the unsigned vector is.

Of course you could write a function to_std_logic_vector. There just 
isn't one in numeric_std (as far as I know).

Author: Lothar Miller (lkmiller) (Moderator)
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Dussel wrote:
> There just isn't one in numeric_std (as far as I know).
No, it isn't. And when the design is done with a little bit thinking 
about structure and layout there are just a few lines with that "double 
step". And the proposed to_std_logic_vector() is just a few letters 
shorter, but it doesn't skip the conversion...

Rejoy M. wrote:
> case d is
> when "111" => o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8));
When you want to assgin a value to a std_logic_vector you can do it with 
"00000001". So why starting with an integer?

Rejoy M. wrote:
> Is there an easier way of doing the same without using Type conversions
> in VHDL. Something like the code below (Although this will return a
> compile error).
> case d is
> when 7 => o <= 1;
Simply implement two local integer signals dl and ol and do it this way:
:
signal dl : integer range 0 to 7;
signal ol : integer range 0 to 255;
:
:
dl <= to_integer(unsigned(d));
:
-- use dl througout the code
:
case dl is
 when 7 => ol <= 1;
:
o <= std_logic_vector(to_unsigned(ol,ol'length));
:

Rejoy M. wrote:
> o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8));
AND AN ADDITIONAL HINT: DO NOT USE CAPITALS AS FUNCTION NAMES. IT MAKES 
THE CODE NEARLY UNREADABLE, BECAUSE THE BRAIN IS IT NOT USED TO READ 
WORDS IN CAPITAL LETTERS!

BTW: pls wrap your VHDL code with the [vhdl] tags...

: Edited by Moderator
Author: Rejoy Mathews (Company: Lab Instructor) (rejoymathews32)
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Lothar,

Thank you so much for all your precise answers and assistance.

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