EmbDev.net

Forum: FPGA, VHDL & Verilog Update a signal and use signal attributes in the same process block


von Rejoy M. (Company: Lab Instructor) (rejoymathews32)


Rate this post
useful
not useful
process
    begin
      clk <= not clk;
      wait for 10ns;
end process;

process(clk)
   begin
     if(clk = '1' and clk'event) then
     --Do something
     end if;
end process;

Presently I am using 2 process blocks to implement the condition above. 
Is there a way I can do it in a single process block?

Something like the code described below. However, the problem with the 
code described below is that the rising edge of the clock is never 
sensed in the simulation. I tried using a blocking assignment 
(variables), but that was not successful either.

I am pretty sure my understanding is missing something. But i cant 
figure out what.

process
   begin
      clk <= not clk;
      wait for 10ns;

     if(clk = '1' and clk'event) then
     --Do something
     end if;
end process;

Thanks in advance.

von Peter (Guest)


Rate this post
useful
not useful
First snippet:
Rejoy M. wrote:
> process(clk)

Second snippet:
Rejoy M. wrote:
> process

You forgot the sensitivity list of the process.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


Rate this post
useful
not useful
Peter wrote:
> You forgot the sensitivity list of the process.
There's a wait in the process, therefore there's no need for a 
sensitivity list

Rejoy M. wrote:
> Is there a way I can do it in a single process block?
Generate the clock without a process:
clk <= not clk after 10ns;

Or do it that way:
process begin
wait for 10ns;
--Do something
end process;

: Edited by Moderator
von No Comment (Guest)


Rate this post
useful
not useful
1
 process(clk)
2
    begin
3
      if rising_edge(clk) then
4
      --Do something
5
      end if;
6
 end process;

von No Comment (Guest)


Rate this post
useful
not useful
Rejoy M. wrote:

> Something like the code described below. However, the problem with the
> code described below is that the rising edge of the clock is never
> sensed in the simulation.

what is the init value of clk?

von Rejoy M. (Company: Lab Instructor) (rejoymathews32)


Rate this post
useful
not useful
No Comment wrote:
> Rejoy M. wrote:
>
>> Something like the code described below. However, the problem with the
>> code described below is that the rising edge of the clock is never
>> sensed in the simulation.
>
> what is the init value of clk?

The initial value of clk is defined as 0

von Rejoy M. (Company: Lab Instructor) (rejoymathews32)


Rate this post
useful
not useful
Thank you for your reply Lothar.

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.