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Forum: FPGA, VHDL & Verilog Update a signal and use signal attributes in the same process block


Author: Rejoy Mathews (Company: Lab Instructor) (rejoymathews32)
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process
    begin
      clk <= not clk;
      wait for 10ns;
end process;

process(clk)
   begin
     if(clk = '1' and clk'event) then
     --Do something
     end if;
end process;

Presently I am using 2 process blocks to implement the condition above. 
Is there a way I can do it in a single process block?

Something like the code described below. However, the problem with the 
code described below is that the rising edge of the clock is never 
sensed in the simulation. I tried using a blocking assignment 
(variables), but that was not successful either.

I am pretty sure my understanding is missing something. But i cant 
figure out what.

process
   begin
      clk <= not clk;
      wait for 10ns;

     if(clk = '1' and clk'event) then
     --Do something
     end if;
end process;

Thanks in advance.

Author: Peter (Guest)
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First snippet:
Rejoy M. wrote:
> process(clk)

Second snippet:
Rejoy M. wrote:
> process

You forgot the sensitivity list of the process.

Author: Lothar Miller (lkmiller) (Moderator)
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Peter wrote:
> You forgot the sensitivity list of the process.
There's a wait in the process, therefore there's no need for a 
sensitivity list

Rejoy M. wrote:
> Is there a way I can do it in a single process block?
Generate the clock without a process:
clk <= not clk after 10ns;

Or do it that way:
process begin
wait for 10ns;
--Do something
end process;

: Edited by Moderator
Author: No Comment (Guest)
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 process(clk)
    begin
      if rising_edge(clk) then
      --Do something
      end if;
 end process;


Author: No Comment (Guest)
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Rejoy M. wrote:

> Something like the code described below. However, the problem with the
> code described below is that the rising edge of the clock is never
> sensed in the simulation.

what is the init value of clk?

Author: Rejoy Mathews (Company: Lab Instructor) (rejoymathews32)
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No Comment wrote:
> Rejoy M. wrote:
>
>> Something like the code described below. However, the problem with the
>> code described below is that the rising edge of the clock is never
>> sensed in the simulation.
>
> what is the init value of clk?

The initial value of clk is defined as 0

Author: Rejoy Mathews (Company: Lab Instructor) (rejoymathews32)
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Thank you for your reply Lothar.

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