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Forum: FPGA, VHDL & Verilog 8-bit counter with enable VHDL


Author: Dmitry Oshkanov (Company: VGTU) (dimsan)
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Hi guys.I need to write code for counter with input ENABLE and 
synchronous reset. The сounter must count up to 19. I have this code, 
but I don't understand where there is an error. Help me please anybody 
=)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity UP_COUNTER is
    Port ( clk: in std_logic; -- clock input
           reset: in std_logic; -- reset input 
           ce: in std_logic; -- enable input
           counter: out std_logic_vector(7 downto 0) -- output 4-bit counter
     );
end UP_COUNTER;

architecture Behavioral of UP_COUNTER is
    signal counter_up: std_logic_vector(7 downto 0);
begin
-- up counter
process(clk)
begin
    if rising_edge(clk) then
        if reset = '1' then
            counter_up <= (others=>'0');
        elsif ce = '1' then
            M1: for i in 0 to 19 
          loop
          counter_up <= counter_up + i;
        end loop;
        end if;
    end if;
 end process;
    counter <= counter_up;            
end Behavioral;

: Edited by Moderator
Author: 2loop|~2loop (Guest)
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Dmitry O. wrote:
> Hi guys.I need to write code for counter with input ENABLE and
> synchronous reset. The сounter must count up to 19. I have this code,
> but I don't understand where there is an error.

The keyword 'loop' marks the lines with errors.

PS:
Ваши английские предложения звучат больше немецкого, чем русского.

Author: Dmitry Oshkanov (Company: VGTU) (dimsan)
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Where is the error? Tell me please

Author: 2loop|~2loop (Guest)
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1) remove/replace everything that belongs to the "loop" construct ->
   you'll end up with a line:
 
    counter_up <= counter_up + 1;  --note the '1' instead of i
2) then simulate and think
 -how to detect the upper bound of the counting range
 -how to set the counter to the lower bound

-> then you will end up with a counter that works.

If you wanna improve your code further, think about an appropriate type 
for the counter_up value i.e. 'unsigned' instead of 'std_logic_vector'. 
And stay improving the code by using type 'integer' with 'range' 
constraint.

Author: Lothar Miller (lkmiller) (Moderator)
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Dmitry O. wrote:
> Where is the error? Tell me please
First: pls wrapp your VHDL code in the VHDL tags
[vhdl]
  VHDL code
[/vhdl]

Second: do not use comments when they tend to be wrong or completely 
needless, such as this
    clk: in std_logic; -- clock input
    reset: in std_logic; -- reset input 
    ce: in std_logic; -- enable input
    counter: out std_logic_vector(7 downto 0) -- output 4-bit counter
Of course "clk: in std_logic" is the "clock input" andsoforth. And then 
(7 downto 0) is 8 bits, not 4 bits!

Third: forget what you know about loops from C or any other 
programming language. A loop in VHDL ist somthing COMPLETELY 
different.

Fourth: do not use the outdated std_logic_arith packages. Use the 
numeric_std instead!
See the conversion chart there 
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

Finally try this and think about it:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity UP_COUNTER is
    Port ( clk: in std_logic;
           reset: in std_logic;
           ce: in std_logic;
           counter: out std_logic_vector(7 downto 0)
     );
end UP_COUNTER;

architecture Behavioral of UP_COUNTER is
    signal counter_up: integer range 0 to 19 := 0;
begin
-- up counter
process(clk)
begin
    if rising_edge(clk) then
        if reset = '1' then
           counter_up <= 0;
        elsif ce = '1' then
           if counter_up<19 then
              counter_up <= counter_up + i;
           else 
              counter_up <= 0;
           end if;
        end if;
    end if;
 end process;
    counter <= std_logic_vector(to_unsigned(counter_up,8));            
end Behavioral;

Author: Dmitry Oshkanov (Company: VGTU) (dimsan)
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Thanks for the explanation

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